參數(shù)資料
型號(hào)： MAX549
廠商： Maxim Integrated Products, Inc.
英文描述： +2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in レMAX Package
中文描述： 2.5V至5.5V，低功耗，單/雙，8位電壓在レmax包裝輸出DAC
文件頁(yè)數(shù)： 3/16頁(yè)
文件大小： 172K
代理商： MAX549
M
+2.5V to +5.5V, Low-Power, S ingle/Dual,
8-Bit Voltage-Output DACs in μMAX Pac kage
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.5V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C)
SYMBOL
PARAMETER
DYNAMIC PERFORMANCE
TIMING CHARACTERISTICS
(V
DD
= +2.5V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Digital inputs switching from 0V to V
DD
.) (Figure 3) (Note 4)
Note 1:
Cold temperature specifications (to -40°C) guaranteed by design using six sigma design limits.
Note 2:
Worst-case input resistance at REF occurs at DAC code 55 hex.
Note 3:
Worst-case reference input current occurs at DAC code 55 hex.
Note 4:
Guaranteed by design. Not production tested.
Note 5:
I
DD
measured with DACs loaded with worst-case DAC code 55 hex.
CS
= high, all digital inputs from 0V to V
DD
C
L
= 20pF
To ±1/2LSB, C
L
= 20pF
V/μs
3.1
4
μs
1.4
Voltage-Output Settling Time
4
CONDITIONS
50
nV-sec
Digital Feedthrough and
Crosstalk
UNITS
MIN
TYP
MAX
Voltage-Output Slew Rate
C
L
= 20pF
μs
Wake-Up Time at Power-Up
POWER SUPPLIES
V
DD
= 2.5V
V
DD
= 5.5V
Supply Voltage Range
Outputs unloaded, all inputs = GND or V
DD
V
DD
V
2.5
5.5
Supply Current
(MAX549A/MAX550A)
Shutdown Current
Outputs unloaded,
all inputs = GND or
V
DD
(Note 5)
μA
330
550
I
DD
Supply Current (MAX548A)
Outputs unloaded, all inputs = GND or V
DD
;
V
DD
= 5.5V
Shutdown mode
I
DD
μA
0.3
10
V
DD
= 5.5V
V
DD
= 2.5V
μA
0.3
150
250
80
50
50
5
SCLK Period
LDAC
Pulse Width Low
t
CP
t
LDAC
CS High to
LDAC
Low
V
DD
High to
CS
Low
ns
ns
t
CSLD
ns
μs
MAX548A/MAX550A only
MAX548A/MAX550A only
40
CS
Pulse Width High
t
CSW
ns
20
t
CSH1
ns
V
DD
= 5.5V
10
30
30
10
t
DH
CS
High to SCLK High Setup
SCLK High to CS Low Hold
ns
t
CSS1
t
CSH0
ns
ns
10
Delay, SCLK High to
CS
High
V
DD
= 2.5V
V
DD
= 5.5V
CS
Low to SCLK High Setup
t
CSS0
ns
30
0
DIN to SCLK High Setup
t
DS
ns
DIN to SCLK High Hold
V
DD
= 2.5V
40
SCLK Pulse Width Low
t
CL
ns
PARAMETER
SYMBOL
t
CH
MIN
40
TYP
MAX
UNITS
ns
CONDITIONS
SCLK Pulse Width High
相關(guān)PDF資料
PDF描述
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