參數(shù)資料
型號(hào)： MAX5295EUE
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????)
中文描述： SERIAL INPUT LOADING, 2 us SETTLING TIME, 8-BIT DAC, PDSO16
封裝： 6.50 X 5 MM, MO-153AB, TSSOP-16
文件頁數(shù)： 7/33頁
文件大?。?/td> 941K
代理商： MAX5295EUE
M
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________
7
TIMING CHARACTERISTICS
—
DSP Mode Disabled (1.8V Logic) (Figure 1) (continued)
(DVDD= 1.8V to 3.6V, DGND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
t
DOZ
C
L
= 20pF, from end of write cycle to UPIO_
in high impedance
200
ns
DOUTRB Tri-State Time from
CS
Rise
t
DRBZ
C
L
= 20pF, from rising edge of
CS
to UPIO_
in high impedance
40
ns
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
t
ZEN
C
L
= 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state
40
ns
LDAC
Pulse-Width Low
LDAC
Effective Delay
CLR
,
MID
,
SET
Pulse-Width Low
GPO Output Settling Time
t
LDL
t
LDS
t
CMS
t
GP
Figure 5
Figure 6
Figure 5
Figure 6
40
200
40
ns
ns
ns
ns
200
GPO Output High-Impedance
Time
t
GPZ
200
ns
TIMING CHARACTERISTICS
—
DSP Mode Enabled (3V, 3.3V Logic) (Figure 2)
(DVDD= 2.7V to 3.6V, DGND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
f
SCLK
t
CH
t
CL
t
CSS
t
DSS
t
CSH
t
CS0
t
DS0
t
DS
t
DH
CONDITIONS
MIN
TYP
MAX
20
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Fall to SCLK Fall Setup Time
DSP
Fall to SCLK Fall Setup Time
SCLK Fall to
CS
Rise Hold Time
SCLK Fall to
CS
Fall Delay
SCLK Fall to
DSP
Fall Delay
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
2.7V < DV
DD
< 3.6V
(Note 7)
(Note 7)
20
20
10
10
5
10
10
12
5
SCLK Rise to DOUT_ Valid
Propagation Delay
t
DO1
C
L
= 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode
30
ns
SCLK Fall to DOUTDC0 Valid
Propagation Delay
t
DO2
C
L
= 20pF, UPIO_ = DOUTDC0 mode
30
ns
CS
Rise to SCLK Fall Hold Time
CS
Pulse-Width High
DSP
Pulse-Width High
DSP
Pulse-Width Low
t
CS1
t
CSW
t
DSW
t
DSPWL
MICROWIRE and SPI modes 0 and 3
10
45
20
20
ns
ns
ns
ns
(Note 8)
相關(guān)PDF資料
PDF描述
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