參數(shù)資料
型號(hào)： MAX5100
廠商： Maxim Integrated Products, Inc.
英文描述： +2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
中文描述： +2.7V至+5.5V、低功耗、四路、并行8位DAC，滿(mǎn)擺幅電壓輸出
文件頁(yè)數(shù)： 7/8頁(yè)
文件大?。?/td> 401K
代理商： MAX5100
When
WR
is low, the addressed DAC’s input latch is
transparent. Data is latched when
WR
is high.
The MAX5100
LDAC
feature allows simultaneous
updating of all four DACs.
LDAC
low latches the data in
the data registers to the DAC registers. If simultaneous
updating is not required, tie
LDAC
low to keep the DAC
latches transparent. If
WR
and
LDAC
are low simultane-
ously, avoid output glitches by ensuring that data is
valid before the two signals go low. When the device
powers up (i.e., V
DD
ramps up), all latches are internal-
ly preset with code 00 hex.
Applications Information
External Reference
The reference source resistance must be considerably
less than the reference input resistance. To keep within
1LSB error in an 8-bit system, R
S
must be less than
R
REF
/ 256. Hence, maintain a value of R
S
<1k
to
ensure 8-bit accuracy. If V
REF
is DC only, bypass REF
to GND with a 0.1μF capacitor. Values greater than this
improve noise rejection.
Power Sequencing
The voltage applied to REF should not exceed V
DD
at
any time. If proper power sequencing is not possible,
connect an external Schottky diode between REF and
V
DD
to ensure compliance with the absolute maximum
ratings.
Power-Supply Bypassing and
Ground Management
Digital or AC transient signals on GND can create noise
at the analog output. Return GND to the highest-quality
ground available. Bypass V
DD
with a 0.1μF capacitor,
located as close to V
DD
and GND as possible.
Careful PC board ground layout minimizes crosstalk
between the DAC outputs and digital inputs.
Chip Information
TRANSISTOR COUNT: 6848
M
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
_______________________________________________________________________________________
7
OUTC
OUTD
MAX5100
DAC C
DAC D
INPUT
LATCH C
DAC C
LATCH
INPUT
LATCH D
DAC D
LATCH
CONTROL
LOGIC
SHDN
REF
A1
AO
D0–D7
WR
LDAC
OUTA
OUTB
DAC A
DAC B
INPUT
LATCH A
DAC A
LATCH
INPUT
LATCH B
DAC B
LATCH
Figure 2. Functional Diagram
H = High state, L = Low state, X = Don’t care
Table 1. MAX5100 Address Table (Partial)
A0
X
L
X
L
H
L
H
A1
X
L
X
L
H
H
L
WR
LATCH STATE
H
H
Input and DAC data latched
H
L
DAC A input latch transparent
LDAC
L
H
All 4 DACs’ DAC latches
transparent
L
L
DAC A input registers transpar-
ent and all 4 DACs’ DAC
latches transparent
H
L
DAC D input latch transparent
H
L
DAC C input latch transparent
H
L
DAC B input latch transparent
相關(guān)PDF資料
PDF描述
MAX5100AEUP +2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MAX5100AEUP+ 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 4Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX5100AEUP+T 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 4Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX5100AEUP-T 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX5100BEUP 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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