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參數(shù)資料
| 型號： | MAX5100 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | +2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs |
| 中文描述： | +2.7V至+5.5V、低功耗、四路、并行8位DAC，滿擺幅電壓輸出 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 401K |
| 代理商： | MAX5100 |
M
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
_______________________________________________________________________________________
3
Note 1:
Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.
Note 2:
Gain error is: [100 (V
F0,meas
- ZCE - V
F0,ideal
) / V
REF
]. Where V
F0,meas
is the DAC output voltage with input code F0 hex,
and V
F0,ideal
is the ideal DAC output voltage with input code F0 hex (i.e., V
REF
·
240 / 256).
Note 3:
Output settling time is measured from the 50% point of the falling edge of
WR
to ±1/2LSB of V
OUT
’s final value.
Note 4:
Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any
other DAC output. The measured channel has a fixed code of 80 hex.
Note 5:
Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight
data inputs with
WR
at V
DD
.
Note 6:
R
L
=
∞
, digital inputs at GND or V
DD
.
Note 7:
Timing measurement reference level is (V
IH
+ V
IL
) / 2.
Note 8:
If
LDAC
is activated prior to
WR
’s rising edge, it must stay low for t
LD
(or longer) after
WR
goes high.
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= V
REF
= +2.7V to +5.5V, R
L
= 10k
, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
DD
= V
REF
= +3V and T
A
= +25°C.)
V
REF(DC)
= 1.5V,
V
DD
= 3V,
code = FF hex
LDAC
Pulse Width (Note 8)
t
LD
20
ns
Digital-to-Analog Glitch Impulse
90
nVs
Digital Feedthrough (Note 5)
0.5
nVs
Channel-to-Channel Isolation
(Note 4)
500
nVs
Output Settling Time (Note 3)
6
μs
Signal-to-Noise plus Distortion
Ratio
SINAD
70
dB
60
Multiplying Bandwidth
650
kHz
Wideband Amplifier Noise
Shutdown Recovery Time
Time to Shutdown
POWER SUPPLIES
60
13
20
μV
RMS
μs
μs
Output Voltage Slew Rate
0.6
V/μs
t
SDR
t
SDN
Power-Supply Voltage
Supply Current (Note 6)
Shutdown Current
DIGITAL TIMING
(Figure 1) (Note 7)
V
DD
I
DD
2.7
5.5
700
1
V
370
0.001
μA
μA
Address to
WR
Setup
Address to
WR
Hold
Data to
WR
Setup
Data to
WR
Hold
WR
Pulse Width
t
AS
t
AH
t
DS
t
DH
t
WR
5
0
25
0
20
ns
ns
ns
ns
ns
To ±1/2LSB of final value of V
OUT
I
DD
< 5μA
Code 80 hex to code 7F hex
Code 00 to code FF hex
Code 00 to code FF hex
To 1/2LSB, from code 10 to code F0 hex
REF = 0.5Vp-p, V
REF(DC)
= 1.5V,
V
DD
= 3V, -3dB bandwidth
From code 00 to code F0 hex
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
REF = 2.5Vp-p at
1kHz
REF = 2.5Vp-p at
10kHz
DYNAMIC PERFORMANCE
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