參數(shù)資料
型號(hào)： MAX500BMJE
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： DAC
英文描述： CMOS, Quad, Serial-Interface 8-Bit DAC
中文描述： SERIAL INPUT LOADING, 2.5 us SETTLING TIME, 8-BIT DAC, CDIP16
封裝： CERAMIC, DIP-16
文件頁(yè)數(shù)： 1/12頁(yè)
文件大?。?/td> 127K
代理商： MAX500BMJE
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
_______________General Desc ription
The MAX500 is a quad, 8-bit, voltage-output digital-to-
analog converter (DAC) with a cascadable serial inter-
face. The IC includes four output buffer amplifiers and
input logic for an easy-to-use, two- or three-wire serial
interface. In a system with several MAX500s, only one
serial data line is required to load all the DACs by cas-
cading them. The MAX500 contains double-buffered
logic and a 10-bit shift register that allows all four DACs
to be updated simultaneously using one control signal.
There are three reference inputs so the range of two of
the DACs can be independently set while the other two
DACs track each other.
The MAX500 achieves 8-bit performance over the full
operating temperature range without external trimming.
________________________Applic ations
Minimum Component Count Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Arbitrary Function Generators
Automatic Test Equipment
____________________________Features
o
Buffered Voltage Outputs
o
Double-Buffered Digital Inputs
o
Microprocessor and TTL/CMOS Compatible
o
Requires No External Adjustments
o
Two- or Three-Wire Cascadable Serial Interface
o
16-Pin DIP/SO Package and 20-Pin LCC
o
Operates from Single or Dual Supplies
______________Ordering Information
M
CMOS , Quad, S erial-Interfac e
8-Bit DAC
________________________________________________________________ Maxim Integrated Products
1
TOP VIEW
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
OUT
C
V
OUT
D
V
DD
V
REF
C
V
REF
A/B
V
SS
V
OUT
A
V
OUT
B
MAX500
V
REF
D
SRO
SCL
LOAD
SDA
LDAC
DGND
AGND
DIP/SO
_________________Pin Configurations
MAX500
V
OUT
A
DAC A
DAC B
DAC C
DAC D
V
REF
C
V
REF
A/B
DAC
REG A
INPUT
REG A
DAC
REG B
INPUT
REG B
DAC
REG C
INPUT
REG C
DAC
REG D
INPUT
REG D
10/11-
BIT
SHIFT
REGISTER
CONTROL
LOGIC
LOAD
SCL
SDA
V
OUT
B
V
OUT
C
V
OUT
D
SRO
V
DD
DGND V
SS
AGND
V
REF
D
D
LDAC
________________Func tional Diagram
19-1016; Rev 2; 2/96
PART
MAX500ACPE
MAX500BCPE
MAX500ACWE
MAX500BCWE
MAX500BC/D
MAX500AEPE -40°C to +85°C
MAX500BEPE -40°C to +85°C
MAX500AEWE
-40°C to +85°C
MAX500BEWE
-40°C to +85°C
MAX500AEJ E
MAX500BEJ E
MAX500AMJ E
-55°C to +125°C
MAX500BMJ E
-55°C to +125°C
MAX500AMLP
-55°C to +125°C
MAX500BMLP
-55°C to +125°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
Dice*
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
16 CERDIP
16 CERDIP
16 CERDIP
16 CERDIP
20 LCC
20 LCC
-40°C to +85°C
-40°C to +85°C
ERROR (LSB)
±1
±2
±1
±2
±2
±1
±2
±1
±2
±1
±2
±1
±2
±1
±2
*Contact factory for dice specifications.
Pin Configurations continued on last page.
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