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參數(shù)資料
| 型號： | MAX500 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | CMOS, Quad, Serial-Interface 8-Bit DAC(電壓輸出,四通道,串行,8位D/A轉(zhuǎn)換器) |
| 中文描述： | CMOS、四路、串行接口8位DAC |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 165K |
| 代理商： | MAX500 |
M
CMOS , Quad, S erial-Interfac e
8-Bit DAC
_______________________________________________________________________________________
5
12
0
0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
2
10
M
V
OUT
(V)
I
S
8
6
4
2
6
10
8
4
14
16
V
SS
= -5V
R
O
200
V
SS
= 0V
10
-6
SUPPLY CURRENT
vs. TEMPERATURE
-4
6
M
TEMPERATURE (°C)
S
0
-2
4
2
8
12
-55
125
25
-25
0
75
50
100
I
DD
I
SS
1.5
-2.0
ZERO-CODE ERROR
vs. TEMPERATURE
-1.5
1.0
M
TEMPERATURE (°C)
Z
0.0
-1.0
0.5
-0.5
2.0
-55
125
25
-25
0
75
50
100
V
SS
= -5V
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
____________________________Typic al Operating Charac teristic s (c ontinued)
_______________Detailed Desc ription
The MAX500 has four matched voltage-output digital-to-
analog converters (DACs). The DACs are “inverted”
R-2R ladder networks which convert 8 digital bits into
equivalent analog output voltages in proportion to the
applied reference voltage(s). Two DACs in the MAX500
have a separate reference input while the other two
DACs share one reference input. A simplified circuit
diagram of one of the four DACs is provided in Figure 1.
V
REF
Input
The voltage at the V
REF
pins (pins 4, 12, and 13) sets
the full-scale output of the DAC. The input impedance
of the V
REF
inputs is code dependent. The lowest
value, approximately 11k
(5.5k
for V
REF
A/B), occurs
when the input code is 01010101. The maximum value
of infinity occurs when the input code is 00000000.
Because the input resistance at V
REF
is code depen-
dent, the DAC’s reference sources should have an out-
put impedance of no more than 20
(no more than
10
for V
REF
A/B). The input capacitance at V
REF
is
also code dependent and typically varies from 15pF to
35pF (30pF to 70pF for V
REF
A/B). V
OUT
A, V
OUT
B,
V
OUT
C, and V
OUT
D can be represented by a digitally
programmable voltage source as:
V
OUT
= N
b
x V
REF
/ 256
where N
b
is the numeric value of the DAC’s binary
input code.
Output Buffer Amplifiers
All voltage outputs are internally buffered by precision
unity-gain followers, which slew at greater than 3V/μs.
When driving 2k
in parallel with 100pF with a full-scale
transition (0V to +10V or +10V to 0V), the output settles
to ±1/2LSB in less than 4μs. The buffers will also drive
2k
in parallel with 500pF to 10V levels without oscilla-
tion. Typical dynamic response and settling perfor-
mance of the MAX500 is shown in Figures 2 and 3.
A simplified circuit diagram of an output buffer is
shown in Figure 4. Input common-mode range to
AGND is provided by a PMOS input structure. The out-
put circuitry incorporates a pull-down circuit to actively
drive V
OUT
to within +15mV of the negative supply
(V
SS
). The buffer circuitry allows each DAC output to
R
R
R
2R
2R
2R
2R
2R
V
REF
AGND
V
OUT
DB0
DB5
DB6
DB7
DB0
DB5
DB6
DB7
…
…
…
Figure 1. Simplified DAC Circuit Diagram
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