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參數(shù)資料
| 型號： | MAX500 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | CMOS, Quad, Serial-Interface 8-Bit DAC(電壓輸出,四通道,串行,8位D/A轉(zhuǎn)換器) |
| 中文描述： | CMOS、四路、串行接口8位DAC |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 165K |
| 代理商： | MAX500 |
M
CMOS , Quad, S erial-Interfac e
8-Bit DAC
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(V
DD
= +11.4V to +16.5V, V
SS
= -5V ±10%, AGND = DGND = 0V, V
REF
= +2V to (V
DD
- 4V), T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Outputs unloaded
V
OUT
= 10V
For specified performance
Outputs unloaded
(Note 5)
(Note 5)
TA = +25°C (Note 2)
To ±1/2LSB, V
REF
= 10V, V
DD
= +15V,
2k
in parallel with 100pF load (Note 2)
CONDITIONS
ns
150
t
LDS
t
LDAC
t
D1
t
1
t
H
t
1
t
2
LOAD
Delay from SCL
LDAC
Pulse Width
ns
150
t
LDW
LOAD
Pulse Width
ns
350
t
2
SCL Low Time
ns
350
t
1
SCL High Time
ns
150
t
S1
t
H
SDA Valid to SCL Setup
ns
150
t
S1
SDA Valid to SCL Setup
mA
-10
I
SS
Negative Supply Current
-9
mA
12
I
DD
Positive Supply Current
10
V
11.4
16.5
V
DD
V
DD
Positive Supply Voltage
k
2
Output Load Resistance
nV-s
50
Digital Crosstalk
nV-s
50
Digital Feedthrough
3
8
Voltage Output Slew Rate
μs
2.5
4.5
V
OUT
Settling Time
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
150
ns
SRO Output Delay
C
LOAD
= 50pF
150
ns
SCL High Time
350
ns
SDA Valid to SCL Hold
0
ns
LDAC
Pulse Width
t
LDAC
t
S1
t
S2
t
S3
t
D1
150
ns
SCL Valid to SDA Setup
Start condition
150
ns
SDA Valid to SCL Setup
Stop condition
100
ns
T
A
= +25°C
T
A
= T
MIN
to T
MAX
T
A
= +25°C
T
A
= T
MIN
to T
MAX
V/μs
SDA Valid to Rising SCL
125
ns
SRO Output Delay
C
LOAD
= 50pF
150
ns
SCL High Time
350
ns
SCL Fall Time
(Note 7)
50
μs
SCL Rise Time
(Note 7)
50
μs
SCL Low Time
350
ns
For specified performance
V
11.4
16.5
Positive Supply Voltage
(Note 7)
μs
50
SCL Rise Time
(Note 7)
μs
50
SCL Fall Time
ns
0
SDA Valid to SCL Hold
DYNAMIC PERFORMANCE
SWITCHING CHARACTERISTICS
(
T
A
= +25°C, Note 6)
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