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參數(shù)資料
| 型號(hào)： | MAX4950ACTX+T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual PCI Express Equalizer/Redriver; Package: TQFN;36 pin;37 mm² ; Temperature: 0°C to +70°C |
| 中文描述： | BUF OR INV BASED PRPHL DRVR, QCC36 |
| 封裝： | 6 X 6 MM, TQFN-36 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 531K |
| 代理商： | MAX4950ACTX+T |
MAX4950A
Dual PCI Express Equalizer/Redriver
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, CCL = 75nF coupling capacitor on each output, RL = 50
Ω resistor on each output, TA = 0°C to +70°C, unless
otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Electrical Idle Detect Threshold
VTX-IDLE-
THRESH
65
95
120
mVP-P
Output Voltage During Electrical
Idle (AC)
VTX-IDLE-
DIFF-AC-P
ABS|VOUT_P - VOUT_M|, f = 500MHz
25
mVP-P
Receiver Detect Pulse
Amplitude (Note 5)
VTX-RCV-
DETECT
Voltage change in positive direction
600
mV
Receiver Detect Pulse Width
100
ns
Receiver Detect Retry Period
200
ns
CONTROL LOGIC (INEQ_1, INEQ_0, ODE_1, ODE_0, EN, RX_DET, O_AMP_)
Input Logic-Level Low
VIL
0.6
V
Input Logic-Level High
VIH
1.4
V
Input Logic Hysteresis
VHYST
130
mV
Input Leakage Current
IIN
VCONTROL_LOGIC = +0.5V or +1.5V
-50
+50
μA
Note 3: All devices are 100% production tested at TA = +70°C. Specifications for all temperature limits are guaranteed by design.
Note 4: Currents are applicable for both PCIe Generation I and Generation II speeds. Table 5 summarizes the predicted power
consumption.
Note 5: Guaranteed by design, unless otherwise noted.
Note 6: Equivalent to the same amount of deemphasis driving the output.
Note 7: Rise and fall times are measured using 20% and 80% levels.
Timing Diagram
VLOW_P-P
PE(dB) = 20
[log(
)]
VHIGH_P-P
VLOW_P-P
VHIGH_P-P
Figure 1. Illustration of Output Deemphasis
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