- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384673 > MAX4455ECQ (MAXIM INTEGRATED PRODUCTS INC) Triple Differential Transceivers 20-SOIC -40 to 85 PDF資料下載
參數(shù)資料
| 型號： | MAX4455ECQ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 畫面疊加 |
| 英文描述： | Triple Differential Transceivers 20-SOIC -40 to 85 |
| 中文描述： | ON-SCREEN DISPLAY IC, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大小： | 663K |
| 代理商： | MAX4455ECQ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
M
Arbitrary Graphics On-Screen Display
Video Generator
14
______________________________________________________________________________________
SHRBEGH, SHRBEGL
Share begin line HI, share begin line LO. This register
pair contains a 9-bit address, which specifies the start-
ing horizontal line to be used from the shared video
frame buffer memory. SHRBEG HI contains only 1 bit,
which resides in the LSB position (bit 0) of the SHRBEG
HI register. The lower 8 bits of the 9-bit address are
specified by SHRBEG LO. Valid shared line numbers
range from 0 to 483 NTSC (511 PAL). The ASYNC flag
in the channel status register controls the time of actual
update, either immediate (asynchronous) or video field
synchronous. SHRBEGH contains the upper bits of the
starting line address and SHRBEGL contains the lower
bits of the line starting address. To allow the entire
value to be changed at once, the internal value of
SHRBEG (which uses both SHRBEGH and SHRBEGL)
is not updated until SHRBEGL is written. A write to
SHRBEGH alone does not trigger an update of the
internal SHRBEG value.
SHRENDH, SHRENDL
This register pair, share end line HI, share end line LO,
contains a 9-bit address, which specifies the ending
horizontal line to be used from the shared video frame
buffer memory. SHREND HI contains only 1 bit, which
resides in the LSB position (bit 0) of the SHREND HI
register. The lower 8 bits of the 9-bit address are speci-
fied by SHREND LO. Valid shared line numbers range
from 0 to 483 visible NTSC (511 PAL). The ASYNC flag
in the channel status register controls the time of actual
update, either immediate (asynchronous) or video field
synchronous. To allow the entire value to be changed
at once, the internal value of SHREND (which uses both
SHRENDH and SHRENDL) is not updated until
SHRENDL is written. A write to SHRENDH alone does
not trigger an update of the internal SHREND value.
The shared memory source channel register is described below:
BIT7
Ch7
BIT0
Ch0
Ch6
Ch5
Ch4
Ch3
Ch2
Ch1
VOFFSET
The channel vertical offset register defaults at power-up
to 128. Values less than 128 shift the image up while
values greater than 128 shift the OSD image down. For
example, changing VOFFSET from 128 to 80 shifts the
image up by approximately 10% of the visible display.
Changing VOFFSET from 128 to 176 shifts the image
down by approximately 10% of the visible display. This
register controls the vertical offset of the OSD graphics
insertion video. The units of VOFFSET are logical lines.
Vertical offset ensures that the first logical OSD graph-
ics line is visible on the video monitor screen. Updates
to VOFFSET can take up to two full frame periods to
take effect.
SHRSRC
Shared memory source channel. A nonzero value in
SHRSRC replaces a horizontal band of display with data
from another channel. When an SHRSRC channel is
selected (nonzero value in the SHRSRC register), the
channel
’
s graphics video is generated from the chan-
nel
’
s memory, except for the horizontal video lines
between (and including) SHRBEGH/L and SHRENDH/L,
which instead comes from the memory channel speci-
fied by the SHRSRC register (see
Applications
Information
for more details on how video memory shar-
ing works). Time of actual update, either immediate
(asynchronous) or field synchronous, is controlled by the
ASYNC flag in the channel command register. Even
channels can only be shared with even channels. Odd
channels can only be shared with odd channels.
Note:
If multiple even or odd channels are set to 1, data
is taken from the lowest even channel and shared with
the higher even channels. This is also true for the odd
channels.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX445CPG | Triple Differential Transceivers 20-SSOP -40 to 85 |
| MAX4504EPA | Low-Voltage, Dual-Supply, SPST, CMOS Analog Switches |
| MAX4504ESA | Low-Voltage, Dual-Supply, SPST, CMOS Analog Switches |
| MAX4504EUK | Low-Voltage, Dual-Supply, SPST, CMOS Analog Switches |
| MAX4503 | Low-Voltage, Dual-Supply, SPST, CMOS Analog Switches |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX4455ECQ+D | 功能描述:視頻開關(guān) IC RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:4 開啟電阻（最大值）:12 Ohms 傳播延遲時間: 開啟時間（最大值）: 關(guān)閉時間（最大值）: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:WQFN-42 封裝:Reel |
| MAX4455ECQ+TD | 功能描述:視頻開關(guān) IC Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:4 開啟電阻（最大值）:12 Ohms 傳播延遲時間: 開啟時間（最大值）: 關(guān)閉時間（最大值）: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:WQFN-42 封裝:Reel |
| MAX4455ECQ-T | 功能描述:視頻開關(guān) IC RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:4 開啟電阻（最大值）:12 Ohms 傳播延遲時間: 開啟時間（最大值）: 關(guān)閉時間（最大值）: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:WQFN-42 封裝:Reel |
| MAX4455EVKIT | 制造商:Maxim Integrated Products 功能描述:ARBITRARY GRAPHICS ON-SCREEN DISPLAY VIDEO GE - Bulk |
| MAX4455EVSYS | 制造商:Maxim Integrated Products 功能描述:ARBITRARY GRAPHICS ON-SCREEN DISPLAY VIDEO GE - Bulk 制造商:Rochester Electronics LLC 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。