參數(shù)資料
型號(hào)： MAX4455ECQ
廠(chǎng)商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： 畫(huà)面疊加
英文描述： Triple Differential Transceivers 20-SOIC -40 to 85
中文描述： ON-SCREEN DISPLAY IC, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, TQFP-100
文件頁(yè)數(shù)： 13/30頁(yè)
文件大?。?/td> 663K
代理商： MAX4455ECQ
M
Arbitrary Graphics On-Screen Display
Video Generator
______________________________________________________________________________________
13
COMMAND
The channel command register allows writing and read-
ing of quad pixel data into external SDRAM memory.
The read and write operations are described below:
Writing 0000 0010 to the COMMAND register caus-
es the pixel data in QPH and QPL to be stored into
external SDRAM memory.
Writing 0000 0001 to the COMMAND register copies
from external SDRAM memory the quad pixels spec-
ified by QPHORIZ/QPLINE into QPH/QPL.
Writing 0000 0011 to COMMAND register causes a
write followed by a readback to verify the data.
ADDRESS
10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111
NAME
QPH
QPL
QPHORIZ
QPLINEH
QPLINEL
LOSALL
MWRITE
CONTROL
Reserved
DESCRIPTION
Quad pixel high data read/write for multiple write
Quad pixel low data read/write for multiple write
Quad pixel within H line address
Quad pixel line address high
Quad pixel line address low
Loss-of-sync flags for channels 0 through 7
Command register, triggers multiple write(s)
Control bits
Reserved registers
10001000 TO 10001111
Table 4. Multichannel Block Register Map (Common to All Eight Channels)
QPLINE
NTSC (VOFFSET = 128)
FIELD, LINE
PAL (VOFFSET = 133)
FIELD, LINE
0 0000 0000
0 0000 0001
Field 1, line 21
Field 2, line 21
Field 1, line 26
Field 2, line 26
0 0000 0010
0 0000 0011
Field 1, line 22
Field 2, line 22
Field 1, line 27
Field 2, line 27
0 1111 1110
0 1111 1111
Field 1, line 148
Field 2, line 148
Field 1, line 153
Field 2, line 153
1 1111 0010
1 1111 1111
Field 2, line 263
—
—
Field 2, line 276
Table 5. QPLINE Mapping
The command register is described below:
BIT7
0
BIT0
READ
0
0
0
0
0
WRITE
HOFFSET
The channel horizontal offset register defaults at power-
up to 128. Values less than 128 shift the OSD image to
the left (as viewed on the display), while values greater
than 128 shift the OSD image to the right. For example,
changing HOFFSET from 128 to 110 shifts the image to
the left by approximately 10% of the visible display.
Changing HOFFSET from 128 to 156 shifts the image to
the right by approximately 10% of the visible display.
The image portion shifted beyond the active video is
automatically blanked on any edge. The units of HOFF-
SET are in quad pixels. Horizontal offset is used to
allow flexibility in the video timing for various video
sources. Horizontal offset ensures that the first logical
OSD pixel is visible on the left-hand edge of the video
monitor screen.
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