參數(shù)資料
型號: MAX3969ETP+
廠商: Maxim Integrated Products
文件頁數(shù): 7/11頁
文件大?。?/td> 0K
描述: IC AMP LIMIT 200MBPS 20-TQFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 75
類型: 限幅放大器
應用: 光纖學網絡
安裝類型: 表面貼裝
封裝/外殼: 20-WFQFN 裸露焊盤
供應商設備封裝: 20-TQFN-EP(4x4)
包裝: 管件
MAX3969
200Mbps SFP Limiting Amplifier
_______________________________________________________________________________________
5
Pin Description
PIN
NAME
FUNCTION
17, 18
VCC
Supply Voltage
19
SQUELCH
Squelch Input. The squelch function disables the data outputs by forcing OUT- low and OUT+ high
when the signal is below the power-detect threshold. Connect to GND or leave unconnected to
disable squelch. Connect to VCC to enable squelch.
20
VTH
Output of Internal Op Amp that Sets Power-Detect Threshold Voltage (Figure 1). Connect a resistor
from VTH to INV (R2) and from INV to ground (R1 = 100k
Ω), to program the desired threshold voltage.
EP
Exposed
Pad
Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and
electrical performance.
OFFSET
CORRECTION
1
O
1.2V
REFERENCE
CIN
IN+
FILTER
VCC
IN-
FWD
CFILTER
CAZ
CZN
CZP
R1
100k
Ω
R2
INV
VTH
VCC
VCCO
GND
OUT-
OUT+
SQUELCH
RSSI
LOS
SD
MAX3969
PECL
TTL
PECL
Figure 1. Functional Diagram
Detailed Description
The MAX3969 contains a series of limiting amplifiers
and power detectors, offset correction, data-squelch
circuitry, TTL buffers for LOS outputs, and PECL output
buffers for signal detect (SD) and data outputs. See
Figure 1 for the functional diagram.
Gain Stages and Offset Correction
A cascade of limiting amplifiers provides approximately
65dB of combined small-signal gain. The large gain
makes the amplifier susceptible to small DC offsets in
the signal path. To correct DC offsets, the amplifier has
an internal feedback loop that acts as a DC autozero
circuit. By correcting the DC offsets, the limiting amplifi-
er sensitivity and power-detector accuracy are
improved.
The offset correction is optimized for data streams with
a 50% duty cycle. A different average duty cycle results
in increased pulse-width distortion and loss of sensitivi-
ty. The offset-correction circuitry is less sensitive to vari-
ations of input duty cycle (for example, the 40% to 60%
duty cycle encountered in 4B/5B coding) when the
input is less than 30mVP-P.
The data inputs must be AC-coupled for the offset cor-
rection loop to function properly. Differential input
impedance is >5k
Ω.
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