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參數(shù)資料
| 型號： | MAX3890ECB |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs |
| 中文描述： | SERIAL TO PARALLEL/PARALLEL TO SERIAL CONVERTER, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, MO-136AJ, TQFP-64 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 155K |
| 代理商： | MAX3890ECB |
M
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________________________________________________________________________________
7
Low-Voltage Differential-Signal
Inputs and Outputs
The MAX3890 has LVDS inputs and outputs for inter-
facing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifi-
cation. This technology uses 250mV to 400mV differ-
ential low-voltage swings to achieve fast transition
times, minimized power dissipation, and noise immu-
nity.
For proper operation, the parallel clock LVDS outputs
(PCLKO+, PCLKO-) require 100
differential DC termi-
nation between the inverting and noninverting outputs.
Do not terminate these outputs to ground.
The parallel data and parallel clock LVDS inputs
(PDI_+, PDI_-, PCLKI+, PCLKI-, RCLK+, RCLK-) are
internally terminated with 100
differential input resis-
tance, and therefore do not require external termina-
tion.
PECL Outputs
The serial-data PECL outputs (SDO+, SDO-, SCLKO+,
SCLKO-) require 50
DC termination to (V
CC
- 2V) (see
the Alternative PECL-Output Termination section).
Current-Mode Logic Outputs
The system loopback outputs (SLBO+, SLBO-) of the
MAX3890 are designed using CML. The configuration
of the MAX3890 current-mode logic (CML) output cir-
cuit includes internal 50
back termination to V
CC
(Figure 3). These outputs are intended to drive a 50
transmission line terminated with a matched load
impedance.
t
SKEW
SERIAL
OUTPUT DATA
(SDO)
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-).
*PDI 15 = D15; PDI14 = D14; ...PDI0 = D0.
THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL
INPUT DATA AND SERIAL OUTPUT DATA.
PARALLEL
INPUT DATA
(PDI_)
VALID PARALLEL DATA*
PCLKI
PCLKO
t
SU
t
H
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
*
Figure 2. Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3890ECB+ | 制造商:Maxim Integrated Products 功能描述:LVDS SERLIZER 0.4V 64TQFP EP - Rail/Tube |
| MAX3890ECB+D | 功能描述:串行器/解串器 - Serdes 3.3V 2.5Gbps SDH/ SONET 16:1 Serial RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3890ECB+T | 制造商:Maxim Integrated Products 功能描述:LVDS SERLIZER 0.4V 64TQFP EP - Tape and Reel |
| MAX3890ECB+TD | 功能描述:串行器/解串器 - Serdes 3.3V 2.5Gbps SDH/ SONET 16:1 Serial RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3890ECB-D | 功能描述:串行器/解串器 - Serdes 3.3V 2.5Gbps SDH/ SONET 16:1 Serial RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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