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參數(shù)資料
| 型號(hào)： | MAX3890ECB |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs |
| 中文描述： | SERIAL TO PARALLEL/PARALLEL TO SERIAL CONVERTER, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, MO-136AJ, TQFP-64 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 155K |
| 代理商： | MAX3890ECB |
M
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________________________________________________________________________________
5
Pin Description
NAME
GND
FUNCTION
1, 17, 33, 48, 49, 63
2, 5, 7, 10, 13,
14, 32, 56, 60, 64
3
4
6
8
Ground
V
CC
+3.3V Supply Voltage
PIN
SLBO-
SLBO+
SOS
SCLKO-
System Loopback Inverting Output. Enabled when SOS is high.
System Loopback Noninverting Output. Enabled when SOS is high.
System Loopback Output Select. System loopback disabled when low.
Inverting PECL Serial Clock Output
12
SDO+
Noninverting PECL Serial-Data Output
Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the
PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
Inverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI
inputs. Note that data is updated on the positive transition of the PCLKI signal.
9
SCLKO+
SDO-
Noninverting PECL Serial Clock Output
Inverting PECL Serial-Data Output
55
PCLKO-
Inverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the over-
head management circuit.
Noninverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal refer-
ence clock to the RCLK inputs.
Inverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference
clock to the RCLK inputs.
54
PCLKO+
Noninverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the
overhead management circuit.
57
RCLK+
59
CLKSET
Reference Clock Rate Programming Pin:
CLKSET = V
CC
: Reference Clock Rate = 155.52MHz
CLKSET = Open: Reference Clock Rate = 77.76MHz
CLKSET = 20k
to GND: Reference Clock Rate = 51.84MHz
CLKSET = GND: Reference Clock Rate = 38.88MHz
Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-.
Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-.
58
RCLK-
61
62
FIL-
FIL+
18, 20, 22, 24, 26,
28, 30, 34, 36, 38,
40, 42, 44, 46, 50, 52
PDI15+ to
PDI0+
Noninverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition.
11
15
PCLKI+
16
PCLKI-
19, 21, 23, 25, 27,
29, 31, 35, 37, 39,
41, 43, 45, 47, 51, 53
PDI15- to
PDI0-
Inverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3890ECB+ | 制造商:Maxim Integrated Products 功能描述:LVDS SERLIZER 0.4V 64TQFP EP - Rail/Tube |
| MAX3890ECB+D | 功能描述:串行器/解串器 - Serdes 3.3V 2.5Gbps SDH/ SONET 16:1 Serial RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3890ECB+T | 制造商:Maxim Integrated Products 功能描述:LVDS SERLIZER 0.4V 64TQFP EP - Tape and Reel |
| MAX3890ECB+TD | 功能描述:串行器/解串器 - Serdes 3.3V 2.5Gbps SDH/ SONET 16:1 Serial RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3890ECB-D | 功能描述:串行器/解串器 - Serdes 3.3V 2.5Gbps SDH/ SONET 16:1 Serial RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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