參數(shù)資料
型號(hào)： MAX3349EA
廠(chǎng)商： Maxim Integrated Products, Inc.
英文描述： USB 2.0 Full-Speed Transceiver with UART Multiplexing Mode
中文描述： USB 2.0全速收發(fā)器，提供UART復(fù)用模式
文件頁(yè)數(shù)： 9/17頁(yè)
文件大?。?/td> 397K
代理商： MAX3349EA
M
USB 2.0 Full-Speed Transceiver with UART
Multiplexing Mode
_______________________________________________________________________________________
9
Detailed Description
The MAX3349EA ±15kV ESD-protected, USB transceiver
provides a full-speed USB interface to a microprocessor or
ASIC. The device supports enumeration, suspend, and
V
BUS
detection. A special UART multiplexing mode routes
external UART signals (Rx and Tx) to D+ and D-, allowing
the use of a shared connector to reduce cost and part count
for mobile devices.
The UART interface allows mobile devices such as PDAs,
cellular phones, and digital cameras to use either UART or
USB signaling through the same connector. The
MAX3349EA features a separate UART voltage supply
input. The MAX3349EA supports a maximum UART
baud rate of 921kbaud.
Upon connection to a USB host, the MAX3349EA
enters USB mode and provides a full-speed USB 2.0
compliant interface through VP, VM, RCV, and
OE
. The
MAX3349EA features internal series resistors on D+
and D-, and an internal 1.5k
pullup resistor to D+ to
allow the device to logically connect and disconnect
from the USB bus while plugged in. A suspend mode is
provided for low-power operation. D+ and D- are pro-
tected from electrostatic discharge (ESD) up to ±15kV.
To ensure full ±15kV ESD protection, bypass V
BUS
to
OE
VP/VM
VP/VM
t
PLZ_SE
t
PZL_SE
t
PHZ_SE
t
PZH_SE
D+/D-
CONNECTED TO GND,
VP/VM CONNECTED
TO PULLUP
D+/D-
CONNECTED TO +3V,
VP/VM CONNECTED
TO PULLDOWN
OE
Figure 5. Receiver Enable and Disable Timing
MAX3349EA
1. ENABLE TIME (D+/D-)
MEASUREMENT
D+/D-
TEST
POINT
C
L
50pF
15k
2. VP/VM TO D+/D-
PROPAGATION DELAY
3. D+/D- RISE/FALL TIMES
Figure 7. Test Circuit for Enable Time, Transmitter Propagation
Delay, and Transmitter Rise/Fall Time
MAX3349EA
TEST
POINT
C
15pF
RCV/VP/VM
1. D+/D- TO RCV/VM/VP
PROPAGATION DELAYS
Figure 8. Test Circuit for Receiver Propagation Delay
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
R
C
1M
R
D
1.5k
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 9. Human Body ESD Test Model
Timing Diagrams (continued)
MAX3349EA
1. DISABLE TIME (D+/D-)
MEASUREMENT
V = 0 FOR t
V = V
TRM
FOR t
PLZ
D+/D-
TEST
POINT
C
L
50pF
220
Figure 6. Test Circuit for Disable Time
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