M
USB On-the-Go Transceiver and Charge Pump
24
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SET COMMAND (ADDRESS 06h)
vbus_drv
vbus_dischrg
1
0
0
0
BEHAVIOR OF MAX3301E
vbus_dischrg
0
1
0
Not affected
vbus_chrg
X
X
1
0
vbus_drv
1
0
0
Not affected
vbus_chrg
0
0
1
Not affected
X
1
0
0
Table 9. V
BUS
Control Logic
BIT NUMBER
0
1
SYMBOL
vbus_vld
sess_vld
CONTENTS
Logic 1 if V
BUS
> V
BUS
valid comparator threshold.
Logic 1 if V
BUS
> session valid comparator threshold.
Logic 1 if V
D+
> dp_hi comparator threshold (D+ assertion during data line pulsing through
SRP method).
2
dp_hi
3
id_gnd
Logic 1 if V
ID_IN
< 0.1 x V
CC
.
Logic 1 if V
D-
> dm_hi comparator threshold (D- assertion during data line pulsing through SRP
method).
4
dm_hi
5
id_float
Logic 1 if V
ID_IN
> 0.9 x V
CC
.
Logic 1 if bdis_acon_en = 1 and the MAX3301E asserts dp_pullup after detecting a B device
disconnect during HNP.
6
bdis_acon
7
cr_int_sess_end
Log c 1 i V
BU S
< sess_end com p ar ator thr eshol d or i V
D +
> cr _i nt com p ar ator thr eshol d ( 0.4V to
0.6V d ep end ng on the val ue of i nt_sour ce ( b 5 of sp eci al uncti on r eg ster 1, see Tab e 14)
Table 10. Interrupt Source Register (Address 08h is Read Only)
BIT NUMBER
SYMBOL
CONTENTS
VALUE AT
POWER-UP
0
vbus_vld
vb us_vl d asser s i a tr ansi i on occur s on thi s cond i on and the ap p op ate
i nter up - hi g h or i nter up l ow enab e b i s set. S ee Tab es 10, 12, and 13.
0
1
sess_vld
sess_vl d asser s i a tr ansi i on occur s on thi s cond i on and the ap p op ate
i nter up - hi g h or i nter up - ow enab e b i s set. S ee Tab es 10, 12, and 13.
0
2
dp_hi
d p _hi asser s i a tr ansi i on occur s on thi s cond i on and the ap p op ate i nter up -
hi g h or i nter up - ow enab e b i s set. S ee Tab es 10, 12, and 13.
0
3
id_gnd
i d _g nd asser s i a tr ansi i on occur s on thi s cond i on and the ap p op ate i nter up -
hi g h or i nter up - ow enab e b i s set. S ee Tab es 10, 12, and 13.
0
4
dm_hi
d m _hi asser s i a tr ansi i on occur s on thi s cond i on and the ap p op ate i nter up -
hi g h or i nter up - ow enab e b i s set. S ee Tab es 10, 12, and 13.
0
5
id_float
i d _fl oat asser s i a tr ansi i on occur s on thi s cond i on and the ap p op ate i nter up -
hi g h or i nter up - ow enab e b i s set. S ee Tab es 10, 12, and 13.
0
6
bdis_acon
b d s_acon asser s i a tr ansi i on occur s on thi s cond i on and the ap p op ate
i nter up - hi g h or i nter up - ow enab e b i s set. S ee Tab es 10, 12, and 13.
0
7
cr_int_sess_end
cr _i nt_sess_end asser s i a tr ansi i on occur s on thi s cond i on and the ap p op ate
i nter up - hi g h or i nter up - ow enab e b i s set. S ee Tab es 10, 12, and 13.
0
Table 11. Interrupt Latch Register Description (Write to Address 0Ah to Set, Write to
Address 0Bh to Clear)