參數(shù)資料
型號: MAX3109ETJ+T
廠商: Maxim Integrated Products
文件頁數(shù): 51/66頁
文件大小: 0K
描述: IC UART
產(chǎn)品培訓(xùn)模塊: Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: *
Dual Serial UART with 128-Word FIFOs
MAX3109
55
Maxim Integrated
Synchronization Delay Register 1 (SynchDelay1)
The SynchDelay1 and SynchDelay2 register contents define the time delay between when the UART receives an
assigned transmitter trigger command and when the UART begins transmission.
Bits 7–0: SDelayx
The SDelayx bits are the 8 LSBs of the delay between when the UART receives an assigned transmitter trigger com-
mand and when the UART begins transmission. The delay is expressed in number of UART bit intervals (1/BaudRate).
The maximum delay is 65,535 bit intervals.
For example, given a baud rate of 230.4kbps, the bit time is 4.34Fs, so the maximum delay is 284ms.
Synchronization Delay Register 2 (SynchDelay2)
The SynchDelay1 and SynchDelay2 register contents define the time delay between when the UART receives an
assigned transmitter trigger command and when the UART begins transmission.
Bits 7–0: SDelayx
The SDelayx bits are the 8 MSBs of the delay between when the UART receives an assigned transmitter trigger com-
mand and when the UART begins transmission. The delay is expressed in number of UART bit intervals (1/BaudRate).
The maximum delay is 65,535 bit intervals.
For example, given a baud rate of 230.4kbps, the bit time is 4.34Fs, so the maximum delay is 284ms.
ADDRESS:
0x21
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
SDelay7
SDelay6
SDelay5
SDelay4
SDelay3
SDelay2
SDelay1
SDelay0
RESET
0
ADDRESS:
0x22
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
SDelay15
SDelay14
SDelay13
SDelay12
SDelay11
SDelay10
SDelay9
SDelay8
RESET
0
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