參數(shù)資料
型號： MAX3109ETJ+T
廠商： Maxim Integrated Products
文件頁數(shù)： 29/66頁
文件大?。?/td> 0K
描述： IC UART
產(chǎn)品培訓(xùn)模塊： Obsolescence Mitigation Program
標準包裝： 2,500
系列： *
Dual Serial UART with 128-Word FIFOs
MAX3109
35
Maxim Integrated
Special Character Interrupt Register (SpclCharInt)
SpclCharInt contains interrupts that are generated when a special character is received, an address is received in
multidrop mode, or a line break occurs.
Bits 7 and 6: No Function
Bit 5: MultiDropInt
The MultiDropInt interrupt is generated when the MAX3109 receives an address character in 9-bit multidrop mode,
enabled in MODE2[6]. MultiDropInt is cleared after SpclCharInt is read. MultiDropInt generates an interrupt in ISR[1]
if enabled by SpclChrIntEn[5].
Bit 4: BREAKInt
The BREAKInt interrupt is generated when a line break (RX_ low for longer than one character length) is detected by
the receiver. BREAKInt is cleared after SpclCharInt is read. BREAKInt generates an interrupt in ISR[1] if enabled by
SpclChrIntEn[4].
Bit 3: XOFF2Int
The XOFF2Int interrupt is generated when both an XOFF2 special character is received and special character detection
is enabled by MODE2[4]. XOFF2Int is cleared after SpclCharInt is read. XOFF2Int generates an interrupt in ISR[1] if
enabled by SpclChrIntEn[3].
Bit 2: XOFF1Int
The XOFF1Int interrupt is generated when both an XOFF1 special character is received and special character detection
is enabled by MODE2[4]. XOFF1Int is cleared after SpclCharInt is read. XOFF1Int generates an interrupt in ISR[1] if
enabled by SpclChrIntEn[2].
Bit 1: XON2Int
The XON2Int interrupt is generated when both an XON2 special character is received and special character detection
is enabled by MODE2[4]. XON2Int is cleared after SpclCharInt is read. XON2Int generates an interrupt in ISR[1] if
enabled by SpclChrIntEn[1].
Bit 0: XON1Int
The XON1Int interrupt is generated when both an XON1 special character is received and special character detection
is enabled by MODE2[4]. XON1Int is cleared after SpclCharInt is read. XON1Int generates an interrupt in ISR[1] if
enabled by SpclChrIntEn[0].
ADDRESS:
0x06
MODE:
COR
BIT
7
6
5
4
3
2
1
0
NAME
—
MultiDropInt
BREAKInt
XOFF2Int
XOFF1Int
XON2Int
XON1Int
RESET
0
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