SPI/I2C UART with 128-Word FIFOs Bit 7: IRQSel Depending on the logic level of t" />
參數(shù)資料
型號: MAX3107ETG+T
廠商: Maxim Integrated Products
文件頁數(shù): 25/52頁
文件大?。?/td> 0K
描述: IC UART SPI/I2C 128 FIFO 24TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
特點: 內(nèi)部振蕩器
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.35 V ~ 3.6 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TQFN-EP(3.5x3.5)
包裝: 標準包裝
其它名稱: MAX3107ETG+TDKR
SPI/I2C UART with 128-Word FIFOs
Bit 7: IRQSel
Depending on the logic level of the IRQSel bit, IRQ has different meanings. After a hardware or software (MODE2[0])
reset, the IRQSel bit is set low and after a short delay, the IRQ output signals the end of the MAX3107’s power-up
sequence. The IRQ is low during power-up and transitions to high when the MAX3107 is ready to be programmed.
IRQSel can then be set high. In this case, IRQ becomes a regular interrupt output that signals pending interrupts, as
indicated in the ISR. Details of the IRQSel are described in the Power-Up and IRQ section.
Bit 6: AutoSleep
Set the AutoSleep bit high to set the MAX3107 to automatically enter low-power sleep mode after a period of no activ-
ity (see the Autosleep Mode section). A STSInt[6]: SleepInt interrupt is generated when the MAX3107 goes to sleep or
wakes up.
Bit 5: ForcedSleep
Set the ForcedSleep bit high to force the MAX3107 into low-power sleep mode (see the Sleep Mode section). The cur-
rent sleep or wake state can be read out through this ForcedSleep bit, even when the UART is in sleep mode.
Bit 4: TrnscvCtrl
This bit enables the automatic transceiver direction control. Set TrnscvCtrl high so that RTS/CLKOUT automatically
controls the transceiver’s transmit/receive enable/disable inputs. Setting TrnscvCtrl high sets RTS/CLKOUT low so
that the transceiver is in receive mode. When the TxFIFO contains data available for transmission, the auto direction
control sets RTS/CLKOUT high before the transmitter sends out the data. When the transmitter is empty, RTS/CLKOUT
is automatically forced low again.
Setup and hold times of RTS/CLKOUT with respect to the TX output can be defined through the HDplxDelay register.
A transmitter empty interrupt ISR[5] is generated when the transmitter is empty.
Bit 3: RTSHiZ
Set the RTSHiZ bit high to three-state RTS/CLKOUT.
Bit 2: TxHiZ
Set the TxHiz bit high to three-state the TX output.
Bit 1: TxDisabl
Set the TxDisabl bit high to disable transmission. If the TxDisabl bit is set high during transmission, the transmitter com-
pletes sending out the current character and then ceases transmission. Data still present in the transmit FIFO remains
in the TxFIFO. The TX output is set to logic-high after transmission.
Bit 0: RxDisabl
Set the RxDisabl bit high to disable the receiver so that the receiver stops receiving data. All data present in the receive
FIFO remains in the RxFIFO.
MODE1 Register
ADDRESS:
0x09
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
IRQSel
AutoSleep
ForcedSleep
TrnscvCtrl
RTSHiZ
TxHiZ
TxDisabl
RxDisabl
RESET
0
Maxim Integrated
31
MAX3107
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