參數(shù)資料
型號: MAX3062EEKA#TG16
廠商: Maxim Integrated Products
文件頁數(shù): 5/17頁
文件大?。?/td> 0K
描述: IC TXRX RS485/422 SGL SOT23-8
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: RS422,RS485
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX3062EEKA#TG16DKR
Hot-Swap Line Transient
The circuit of Figure 11 shows a typical offset termina-
tion used to guarantee a greater than 200mV offset
when a line is not driven (the 50pF represents the mini-
mum parasitic capacitance that would exist in a typical
application). During a hot-swap event when the driver
is connected to the line and is powered up, the driver
must not cause the differential signal to drop below
200mV. Figures 12, 13, and 14 show the results of the
MAX3060E during power-up for three different VCC
ramp rates (0.1V/s, 1V/s, and 10V/s). The photos
show the VCC ramp, the single-ended signal on each
side of the 100
Ω termination, as well as the differential
signal across the termination.
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against ESD
encountered during handling and assembly. The
MAX3060E family’s receiver inputs/driver outputs (A, B)
have extra protection against static electricity found in
normal operation. Maxim’s engineers developed state-
of-the-art structures to protect these pins against
±15kV ESD without damage. After an ESD event, the
devices continue working without latchup.
ESD protection can be tested in several ways. The
receiver inputs are characterized for protection to the
following:
±15kV using the Human Body Model
±7kV using the Contact Discharge method specified
in IEC 1000-4-2 (formerly IEC 801-2)
±7kV using the Air-Gap Discharge method specified
in IEC 1000-4-2 (formerly IEC 801-2)
MAX3060E/MAX3061E/MAX3062E
±15kV ESD-Protected, Fail-Safe, 20Mbps, Slew-Rate-
Limited RS-485/RS-422 Transceivers in a SOT
______________________________________________________________________________________
13
MAX3060E/MAX3061E/MAX3062E
DI
5.0V
VCC
0.1k
Ω
1k
Ω
1k
Ω
VCC OR GND
A
B
50pF
Figure 11. Typical Offset Termination
40
μs/div
5V
238mV
20mV/div
200mV/div
0
200mV/div
B
VCC
A
A - B
Figure 12. Differential Power-Up Glitch (0.1V/s)
2
μs/div
B
VCC
238mV
20mV/div
5V
A
A - B
20mV/div
0
Figure 13. Differential Power-Up Glitch (1V/s)
200ns/div
B
VCC
238mV
20mV/div
5V
A
A - B
50mV/div
0
Figure 14. Differential Power-Up Glitch (10V/s)
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