參數(shù)資料
型號(hào): MAX3062EEKA#TG16
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 4/17頁(yè)
文件大?。?/td> 0K
描述: IC TXRX RS485/422 SGL SOT23-8
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: RS422,RS485
電源電壓: 4.75 V ~ 5.25 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX3062EEKA#TG16DKR
MAX3060E/MAX3061E/MAX3062E
±15kV ESD-Protected, Fail-Safe, 20Mbps, Slew-Rate-
Limited RS-485/RS-422 Transceivers in a SOT
12
______________________________________________________________________________________
Hot-Swap Capability
Hot-Swap Input
When circuit boards are inserted into a hot or powered
backplane, differential disturbances to the data bus can
lead to data errors. Upon initial circuit board insertion, the
data communication processor undergoes its own power-
up sequence. During this period, the processor’s logic-
output drivers are high impedance and are unable to
drive the DE and RE inputs of the MAX306_E to a defined
logic level. Leakage currents up to
±10A from the high-
impedance state of the processor’s logic drivers could
cause standard CMOS enable inputs of a transceiver to
drift to an incorrect logic level. Additionally, parasitic cir-
cuit board capacitance could cause coupling of VCC or
GND to the enable inputs. Without the hot-swap capabili-
ty, these factors could improperly enable the transceiver’s
driver or receiver.
When VCC rises, an internal pulldown circuit holds DE
low for at least 10s and until the current into DE
exceeds 200A. After the initial positive transition, the
pulldown circuit becomes transparent, resetting the
hot-swap tolerable input.
Hot-Swap Input Circuitry
These devices’ enable inputs feature hot-swap capabili-
ty. At the input there are two NMOS devices, M1 and M2
(Figure 10). When VCC ramps from zero, an internal 10s
timer turns on M2 and sets the SR latch, which also turns
on M1. Transistors M2, a 300A current sink, and M1, a
30A current sink, pull DE to GND through an 8k
Ω resis-
tor. M2 is designed to pull DE to the disabled state
against an external parasitic capacitance up to 100pF
that can drive DE high. After 10s, the timer deactivates
M2 while M1 remains on, holding DE low against three-
state leakages that can drive DE high. M1 remains on
until an external source overcomes the required input
current. At this time, the SR latch resets and M1 turns off.
When M1 turns off, DE reverts to a standard, high-
impedance CMOS input. Whenever VCC drops below
1V, the hot-swap input is reset.
For RE, there is a complementary circuit employing two
PMOS devices pulling RE to VCC.
Functional Tables
Table 1. Transmitter Functional Table
Table 2. Receiver Functional Table
X = Don’t care.
*Shutdown mode, driver and receiver outputs are high impedance.
TRANSMITTING
INPUTS
OUTPUTS
RE
DE
DI
B
A
X
1
101
X
1
010
0
X
High-Z
1
0
X
Shutdown*
RECEIVING
INPUTS
OUTPUT
RE
DE
A-B
RO
0X
≥ -0.05V
1
0X
≤ -0.2V
0
X
Open/shorted
1
X
High-Z
1
0
X
Shutdown
VCC
TIMER
DE
(HOT SWAP)
10
μs
30
μA
M1
M2
8k
Ω
300
μA
SR LATCH
Figure 10. Simplified Structure of the Driver Enable Input (DE)
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