參數(shù)資料
型號(hào): MAX2079CXE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 25/49頁(yè)
文件大小: 0K
描述: IC OCT ULTRASOUND RCVR 144CTBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: *
Low-Power, High-Performance, Fully Integrated
Octal Ultrasound Receiver (Octal LNA, VGA,
AAF, ADC, and CWD Beamformer)
MAX2079
31
Maxim Integrated
System Timing Requirements
Figure 17 shows the relationship between the analog
inputs, input clock, frame-alignment output, serial-clock
output, and serial-data outputs. The differential ADC
input signal is sampled on the rising edge of the applied
clock signal (CLKIN+, CLKIN-), and the resulting data
appears at the digital outputs 10.5 clock cycles later.
Figure 18 provides a detailed, two-conversion timing
diagram of the relationship between inputs and outputs.
Figure 17. ADC Timing (Overall)
Figure 18. ADC Timing (Detail)
IN_+ - IN_-
CLKIN+
- CLKIN-
CLKOUT+
- CLKOUT-
OUT_+
- OUT_-
FRAME+
- FRAME-
tSAMPLE
N - 10
N - 9N - 8N - 7N - 6N - 5N - 4N - 3N - 2N - 1N
OUTPUT
DATA
FRAME
N
N + 1
N + 2
N + 3N + 4N + 5
10.5 CLOCK-CYCLE DATA LATENCY
N + 6N + 7N + 8
N + 9
N + 10
tSAMPLE
tSF
tDF
N
N + 1
D7N-9
D0N-8
D11N-9
D10N-9
D1N-8 D2N-8 D3N-8 D4N-8 D5N-8 D6N-8 D7N-8 D8N-8 D9N-8 D10N-8D11N-8
D9N-9
D8N-9
D0N-7
D1N-9 D2N-9 D3N-9 D4N-9 D5N-9 D6N-9
IN_+ - IN_-
CLKIN+
- CLKIN-
CLKOUT+
- CLKOUT-
OUT_+
- OUT_-
FRAME+
- FRAME-
tSAMPLE—SAMPLE PERIOD
tDF—FRAME_ RISE TO CLKOUT_ RISE
tSF—SAMPLE CLKIN_ RISE TO FRAME RISE
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