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參數(shù)資料
| 型號： | MAX2079CXE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OCT ULTRASOUND RCVR 144CTBGA |
| 標準包裝： | 1,000 |
| 系列： | * |
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Low-Power, High-Performance, Fully Integrated
Octal Ultrasound Receiver (Octal LNA, VGA,
AAF, ADC, and CWD Beamformer)
MAX2079
25
Maxim Integrated
Figure 4. Simplified Clock Input Schematic
Power-Down and Low-Power Mode
The device can also be powered down with the SHDN
pin. Set SHDN to +1.8V to place the device in power-
down mode. In power-down mode, the device draws a
total supply current less than 1FA from the 5V and 3.3V
supplies, and less than 0.4mA from the 1.8V supplies.
Set SHDN to logic-low for normal operation.
A low-power mode is available to lower the required
power for CWD operation. When selected, the complex
mixers operate at lower quiescent currents. Note that
operation in this mode slightly reduces the dynamic per-
formance of the device. Table 6 shows the logic function
of the standard operating modes.
In addition to power-down mode, the device can be
placed into a reduced-power Standby or Nap mode,
which allows for rapid power-up in VGA mode. Nap mode
is accessable by setting the SHDN pin to +1.8V, with the
ADC_NAP_SHDN1 and AFE_NAP_SHDN1 registers set
to 1 (see Table 6). Nap mode is not meant to be used
in conjunction with CWD mode; valid CWD power states
are normal CWD low-power and power-down modes.
Although no device damage occurs, programming the
device for Nap mode and setting the SHDN pin high can
create invalid signal outputs in CWD mode.
CLKIN+
SELECT
THRESHOLD
AVDD
10kI
20kI
5kI
50I
CLKIN-
INPUT COMMON-MODE
SELF-BIAS BLOCK
CLKIN_INTERNAL 100I
TERMINATION, PROGRAMMED: 04h[4]
DIFFERENTIAL-TO-SINGLE-ENDED
CLOCK CONVERSION
SINGLE-ENDED CLOCK
MODE: INVERTER PATH
SELECT
2:1 MUX
DIFFERENTIAL MODE: CLKIN- > SELECT THRESHOLD
SINGLE-ENDED MODE: CLKIN- < SELECT THRESHOLD
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