參數(shù)資料
型號(hào): MAX1999EEI
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 穩(wěn)壓器
英文描述: High-Efficiency, Quad Output, Main Power- Supply Controllers for Notebook Computers
中文描述: DUAL SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDSO28
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-28
文件頁數(shù): 30/32頁
文件大?。?/td> 497K
代理商: MAX1999EEI
M
High-Effic ienc y, Quad Output, Main Power-
S upply Controllers for Notebook Computers
30
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PGND5). Avoid the introduction of AC currents into
the PGND3 and PGND5 ground planes. Run the
power plane ground currents on the top side only, if
possible.
Use a star ground connection on the power plane to
minimize the crosstalk between OUT3 and OUT5.
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces must be approached in terms of
fractions of centimeters, where a single milliohm of
excess trace resistance causes a measurable effi-
ciency penalty.
CS_ (MAX1777/MAX1977) / LX_ (MAX1999) and GND
connections to the synchronous rectifiers for current
limiting must be made using Kelvin sense connec-
tions to guarantee the current-limit accuracy. With 8-
pin SO MOSFETs, this is best done by routing power
to the MOSFETs from outside using the top copper
layer, while connecting CS_/LX_ traces inside (under-
neath) the MOSFETs.
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the syn-
chronous rectifier or between the inductor and the
output filter capacitor.
Ensure that the OUT_ connection to C
OUT_
is short and
direct. However, in some cases it may be desirable to
deliberately introduce some trace length between the
OUT_ connector node and the output filter capacitor
(see the
Stability Considerations
section).
Route high-speed switching nodes (BST_, DH_, LX_,
and DL_) away from sensitive analog areas (REF,
ILIM_, and FB_). Use PGND3 and PGND5 as an EMI
shield to keep radiated switching noise away from the
IC’s feedback divider and analog bypass capacitors.
Make all pin-strap control input connections (
SKIP
,
ILIM_, etc.) to GND or V
CC
of the device.
Layout Proc edure
1) Place the power components first with ground ter-
minals adjacent (N2/N4 source, C
IN_
, C
OUT_
, D1
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the synchronous
rectifier MOSFETs, preferably on the back side in
order to keep DH_, GND, and the DL_ gate drive
lines short and wide. The DL_ gate trace must be
short and wide measuring 50mils to 100mils wide if
the MOSFET is 1in from the controller device.
3) Group the gate-drive component (BST_ diode and
capacitor, V+ bypass capacitor) together near the
controller device.
AGND
PGND
VIA TOOUT5
GROUND
OUT3
OUT5
VIA TOOUT3
VIA TOPGND
VIA TOLX5
V+
VIA TOLX3
USE AGND PLANE TO:
- BYPASS V
AND REF
- TERMINATE EXTERNAL FB
DIVIDER (IF USED)
- TERMINATE R
ILIM
(IF USED)
- PIN-STRAP CONTROL
INPUTS
USE PGND PLANE TO:
- BYPASS LDO_
- CONNECT PGND TOTHE TOPSIDE STAR GROUND
VIA BETWEEN POWER
AND ANALOG GROUND
VIAS TOGROUND
NOTE:
EXAMPLE SHOWN IS FOR DUAL N-CHANNEL MOSFET.
ANALOG GROUND
PLANE ON INNER LAYER
C4
C3
C1
N4
D
D
N2
C2
L1
L2
CONNECT PGND TOAGND
BENEATH THE CONTROLLER AT
ONE POINT ONLY AS SHOWN.
N3
N1
Figure 13. PC Board Layout Example
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