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參數(shù)資料
| 型號(hào)： | MAX19711ETN+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 21/36頁 |
| 文件大小： | 0K |
| 描述： | IC ANLG FRNT END 56-TQFN |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Jun/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 2 |
| 功率（瓦特）： | 37.5mW |
| 電壓 - 電源，模擬： | 3V |
| 電壓 - 電源，數(shù)字： | 3V |
| 封裝/外殼： | 56-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-TQFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
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MAX19711
10-Bit, 11Msps, Full-Duplex
Analog Front-End
28
______________________________________________________________________________________
the system CLK frequency supplied to the MAX19711
(see Table 17). The total conversion time (tCONV) of the
auxiliary ADC can be calculated as tCONV = (12 x
NAVG x NDIV) / fCLK; where NAVG is the number of
averages (see Table 16), NDIV is the CLK divisor (see
Table 17), and fCLK is the system CLK frequency.
Reading DOUT from the Aux-ADC
DOUT is normally in a high-impedance condition. Upon
setting the auxiliary ADC start conversion bit (bit AD0),
DOUT becomes active and goes high, indicating that
the aux-ADC is busy. When the conversion cycle is
complete (including averaging), the data is placed into
an output register and DOUT goes low, indicating that
the output data is ready to be driven onto DOUT. When
bit AD10 is set (AD10 = 1), the aux-ADC enters a data
output mode where data is available at DOUT on the
next low assertion of CS/WAKE. The auxiliary ADC data
is shifted out of DOUT (MSB first) with the data transi-
tioning on the falling edge of the serial clock (SCLK).
Since a DOUT read requires 16 bits, DOUT holds the
value of the last conversion data bit for the last 6 bits (6
least significant bits) following the aux-ADC conversion
data. DOUT enters a high-impedance state when
CS/WAKE is deasserted high. When bit AD10 is cleared
(AD10 = 0), the aux-ADC data is not available on DOUT
(see Table 18).
After the aux-ADC completes a conversion, the data
result is loaded to an output register waiting to be shift-
ed out. No further conversions are possible until data is
shifted out. This means that if the first conversion com-
mand sets AD10 = 0, AD0 = 1, then it cannot be fol-
lowed by conversion commands setting AD10 = 0, AD0
= 1 or AD10 = 1, AD0 = 1. If this sequence of com-
mands is inadvertently used then DOUT is disabled. To
resume normal operation set AD0 = 0.
The fastest method to perform sequential conversions
with the aux-ADC is by sending consecutive commands
setting AD10 = 1, AD0 = 1. With this sequence the
CS/WAKE falling edge shifts data from the previous con-
version on to DOUT and the rising edge of CS/WAKE
loads the next conversion command at DIN. Allow
enough time for each conversion to complete before
sending the next conversion command. See Figure 9 for
single and continuous conversion examples.
DIN can be written independent of DOUT state. A 16-
bit instruction at DIN updates the device configuration.
To prevent modifying internal registers while reading
data from DOUT, hold DIN at a high state (only applies
if sequential aux-ADC conversions are not executed).
This effectively writes all ones into address 1111. Since
address 1111 does not exist, no internal registers are
affected.
Reference Configurations
The MAX19711 features an internal precision 1.024V-
bandgap reference that is stable over the entire power-
supply and temperature ranges. The REFIN input
provides two modes of reference operation. The volt-
age at REFIN (VREFIN) sets the reference operation
mode (Table 19).
In internal reference mode, connect REFIN to VDD.
VREF is an internally generated 0.512V ±4% reference
level. COM, REFP, and REFN are low-impedance out-
puts with VCOM = VDD / 2, VREFP = VDD / 2 + VREF / 2,
and VREFN = VDD / 2 - VREF / 2. Bypass REFP, REFN,
and COM each with a 0.33F capacitor. Bypass REFIN
to GND with a 0.1F capacitor.
In buffered external reference mode, apply 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with VCOM = VDD / 2,
VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 -
VREFIN / 4. Bypass REFP, REFN, and COM each with a
0.33F capacitor. Bypass REFIN to GND with a 0.1F
capacitor. In this mode, the Tx path full-scale output is
proportional to the external reference. For example, if
the VREFIN is increased by 10% (max), the Tx path full-
scale output is also increased by 10% or ±451mV.
Table 18. Auxiliary ADC Data Output Mode
AD10
SELECTION
0
Aux-ADC Data is Not Available on DOUT (Default)
1
Aux-ADC Enters Data Output Mode Where
Data is Available on DOUT
Table 19. Reference Modes
VREFIN
REFERENCE MODE
> 0.8V x VDD
Internal Reference Mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each
with a 0.33F capacitor.
1.024V ±10%
Buffered External Reference Mode. An external 1.024V ±10% reference voltage is applied to REFIN. VREF is
internally generated to be VREFIN / 2. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass
REFIN to GND with a 0.1F capacitor.
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參數(shù)描述 |
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| MAX19711EVCMODU+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX19710/13 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19711EVKIT | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19711EVKIT+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX19710/13 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19712ETN | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19712ETN+ | 功能描述:ADC / DAC多通道 22Msps CODEC/AFE Full Duplex RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
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