參數(shù)資料
型號: MAX19700ETM+T
廠商: Maxim Integrated Products
文件頁數(shù): 6/32頁
文件大?。?/td> 0K
描述: IC ANLG FRNT END 48-TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 10
通道數(shù): 2
功率(瓦特): 36.3mW
電壓 - 電源,模擬: 3V
電壓 - 電源,數(shù)字: 3V
封裝/外殼: 48-WFQFN 裸露焊盤
供應商設(shè)備封裝: 48-TQFN-EP(7x7)
包裝: 帶卷 (TR)
MAX19700
7.5Msps, Ultra-Low-Power
Analog Front-End
14
______________________________________________________________________________________
PIN
NAME
FUNCTION
1
REFP
Upper Reference Voltage. Bypass with a 0.33F capacitor to GND as close to REFP as possible.
2, 8, 11, 31,
33, 39 43
VDD
Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2F capacitor in parallel with
a 0.1F capacitor.
3
IAP
Channel IA Positive Analog Input. For single-ended operation, connect signal source to IAP.
4
IAN
Channel IA Negative Analog Input. For single-ended operation, connect IAN to COM.
5, 7, 12, 32, 42
GND
Analog Ground. Connect all GND pins to ground plane.
6
CLK
Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs.
9
QAN
Channel QA Negative Analog Input. For single-ended operation, connect QAN to COM.
10
QAP
Channel QA Positive Analog Input. For single-ended operation, connect signal source to QAP.
13–18, 21–24
D0–D9
Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode. D9 is the most
significant bit (MSB) and D0 is the least significant bit (LSB).
19
OGND
Output-Driver Ground
20
OVDD
Output-Driver Power Supply. Supply range from +1.8V to VDD to accommodate most logic levels.
Bypass OVDD to OGND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor.
25
SHDN
Active-Low Shutdown Input. Apply logic-low to place the MAX19700 in shutdown.
26
DR
Data-Ready Indicator. This digital output indicates channel I data (DR = 1) or channel Q data
(DR = 0) is present on the output.
27
T/R
Transmit- or Receive-Mode Select Input. T/R logic-low input sets the device in receive mode. A
logic-high input sets the device in transmit mode.
28
DIN
3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK.
29
SCLK
3-Wire Serial-Interface Clock Input
30
CS
3-Wire Serial-Interface Chip-Select Input. Logic-low enables the serial interface.
34, 35
N.C.
No Connection
36
DAC3
Analog Output for Auxiliary DAC3
37
DAC2
Analog Output for Auxiliary DAC2
38
DAC1
Analog Output for Auxiliary DAC1 (AFC DAC, VOUT = 1.1V During Power-Up)
40, 41
IDN, IDP
DAC Channel-ID Differential Voltage Output
44, 45
QDN, QDP
DAC Channel-QD Differential Voltage Output
46
REFIN
Reference Input. Connect to VDD for internal reference.
47
COM
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33F capacitor.
48
REFN
Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a
0.33F capacitor.
EP
Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
Pin Description
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Detailed Description
The MAX19700 integrates a dual 10-bit Rx ADC and a
dual 10-bit Tx DAC with TD-SCDMA baseband filters
while providing ultra-low power and high dynamic per-
formance at a 7.5Msps conversion rate. The Rx ADC
analog input amplifiers are fully differential and accept
1VP-P full-scale signals. The Tx DAC analog outputs are
fully differential with ±410mV full-scale output, selec-
table common-mode range and offset adjust.
The MAX19700 includes a 3-wire serial interface to
control operating modes and power management. The
serial interface is SPI and MICROWIRE compatible.
The MAX19700 serial interface selects shutdown, idle,
standby, transmit (Tx), and receive (Rx) modes.
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