參數(shù)資料
型號: MAX19700ETM+T
廠商: Maxim Integrated Products
文件頁數(shù): 16/32頁
文件大?。?/td> 0K
描述: IC ANLG FRNT END 48-TQFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 10
通道數(shù): 2
功率(瓦特): 36.3mW
電壓 - 電源,模擬: 3V
電壓 - 電源,數(shù)字: 3V
封裝/外殼: 48-WFQFN 裸露焊盤
供應商設備封裝: 48-TQFN-EP(7x7)
包裝: 帶卷 (TR)
controlled through the SPI bus, except during SHDN
mode where the aux-DACs are turned off completely
and the output voltage is set to zero. In STBY and IDLE
modes the aux-DACs maintain the last value. On wakeup
from SHDN, the aux-DACs resume the last values.
Loading on the aux-DAC outputs should be carefully
observed to achieve specified settling time and stabili-
ty. The capacitive load must be kept to a maximum of
5pF including package and trace capacitance. The
resistive load must be greater than 200k. If capacitive
loading exceeds 5pF, then add a 10k resistor in
series with the output. Adding the series resistor helps
drive larger load capacitance (<15pF) at the expense
of slower settling time.
Reference Configurations
The MAX19700 features an internal precision 1.024V
bandgap reference that is stable over the entire power-
supply and temperature ranges. The REFIN input pro-
vides two modes of reference operation. The voltage at
REFIN (VREFIN) sets the reference operation mode
(Table 11).
In internal reference mode, connect REFIN to VDD.
VREF is an internally generated 0.512V ±4%. COM,
REFP, and REFN are low-impedance outputs with
VCOM = VDD / 2, VREFP = VDD / 2 + VREF / 2, and
VREFN = VDD / 2 - VREF / 2. Bypass REFP, REFN, and
COM each with a 0.33F capacitor. Bypass REFIN to
GND with a 0.1F capacitor.
In buffered external reference mode, apply 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with VCOM = VDD / 2,
VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 -
VREFIN / 4. Bypass REFP, REFN, and COM each with a
0.33F capacitor. Bypass REFIN to GND with a 0.1F
MAX19700
7.5Msps, Ultra-Low-Power
Analog Front-End
______________________________________________________________________________________
23
Table 9. Offset Control Bits for I and Q Channels (IOFFSET or QOFFSET Mode)
BITS IO5–IO0 WHEN IN IOFFSET MODE, BITS QO5–QO0 WHEN IN QOFFSET MODE
IO5/QO5
IO4/QO4
IO3/QO3
IO2/QO2
IO1/QO1
IO0/QO0
OFFSET 1 LSB =
(VFSP-P/1023)
1
-31 LSB
1
0
-30 LSB
1
0
1
-29 LSB
100
010
-2 LSB
100
001
-1 LSB
100
000
0mV
0
0mV (Default)
000
001
1 LSB
000
010
2 LSB
011
101
29 LSB
011
110
30 LSB
011
111
31 LSB
Note: For transmit full-scale select of 820mVP-P: 1 LSB = (820mVP-P/1023) = 0.8016mV. For transmit full-scale select of 1VP-P: 1 LSB
= (1VP-P/1023) = 0.9775mV.
Table 10. Common-Mode Select (COM-
SEL Mode)
CM1
CM0
Tx-PATH OUTPUT COMMON MODE (V)
0
1.4 (Default)
0
1
1.25
1
0
1.1
1
0.9
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