M
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
16
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The actual microfarad capacitance value required
relates to the physical size needed to achieve low ESR,
as well as to the chemistry of the capacitor technology.
As a result, the capacitor is usually selected by ESR
and voltage rating rather than by capacitance value
(this is true of tantalums, OS-CONs, POSCAPs, and
other electrolytics).
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
RMS
) imposed by the switching currents.
Nontantalum chemistries (ceramic, aluminum, or OS-
CON) are preferred due to their superior surge current
capacity:
Setting the Current Limit
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at I
LOAD(MAX)
minus
half of the ripple current. For example:
I
LIMIT(LOW)
> I
LOAD(MAX)
- (LIR / 2)
I
LOAD(MAX)
where I
LIMIT(LOW)
= minimum current-limit threshold
voltage divided by the R
DS(ON)
of Q2. For the
MAX1917, the minimum current-limit threshold (100mV
default setting) is 50mV. Use the worst-case maximum
value for R
DS(ON)
from the MOSFET Q2 data sheet, and
add some margin for the rise in R
DS(ON)
with tempera-
ture. A good general rule is to allow 0.5% additional
resistance for each
°
C of temperature rise.
When adjusting the current limit, use a 1% tolerance
R
ILIM
resistor to prevent a significant increase of errors
in the current-limit tolerance.
Setting the Voltage Positioning
The droop resistor, R
DRP
, in series with the output
inductor before the output capacitor, sets the droop
voltage, V
DRP
. Choose R
DRP
such that the output volt-
age at the maximum load current, including ripple, is
just above the lower limit of the output tolerance:
R
DRP
introduces some power dissipation, which is
given by:
PD(DRP) = R
DRP
I
OUT(MAX)2
R
DRP
should be chosen to handle this power dissipation.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty-factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
input voltage:
PD(Q1) = (V
OUT
/ V
IN(MIN)
)
(I
LOAD2
)
(R
DS(ON)
)
Generally, a small high-side MOSFET is desired in order
to reduce switching losses at high input voltages.
However, the R
DS(ON)
required to stay within package
power-dissipation limits often limits how small the
MOSFET can be. Again, the optimum occurs when the
switching (AC) losses equal the conduction (R
DS(ON)
)
losses. Calculating the power dissipation in Q1 due to
switching losses is challenging because it must allow for
difficult-to-quantify factors that influence the turn-on and
turn-off times. These factors include the internal gate
resistance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The fol-
lowing switching loss calculation provides only a very
rough estimate and is no substitute for breadboard eval-
uation, preferably including a check using a thermocou-
ple mounted on Q1:
where C
RSS
is the reverse transfer capacitance of Q1
and I
GATE
is the peak gate-drive source/sink current.
For the low-side MOSFET, Q2, the worst-case power
dissipation always occurs at maximum input voltage:
PD(Q2) = (1 - V
OUT
/ V
IN(MAX)
)
I
LOAD2
R
DS(ON)
PD SWITCHING
(
C
V
f
I
I
RSS
IN MAX
(
LOAD
GATE
)
)
=
×
× ×
2
R
V
V
I
OUT MAX
(
V
DRP
OUT TYP
(
OUT MIN
(
RIPPLE
<
)
)
)
/
2
I
I
V
V
V
V
RMS
LOAD
OUT
IN
OUT
IN
=
×
×
(
)