M
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
______________________________________________________________________________________
11
Voltage Reference
The voltage at REF is nominally 2.00V. Connect a 0.22μF
ceramic bypass capacitor between REF and GND.
Overcurrent Protection
The current-limit circuit employs a unique
“
valley
”
cur-
rent-sensing algorithm that uses the on-state resistance
of the low-side MOSFET as a current-sensing element.
If the current-sense signal is greater than the current-
limit threshold, the PWM is not allowed to initiate a new
cycle. The actual peak current is greater than the cur-
rent-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit charac-
teristic and maximum load capability are a function of
the MOSFET on-resistance, inductor value, and input
voltage. The reward for this uncertainty is robust, loss-
less overcurrent sensing. There is also a negative cur-
rent limit that prevents excessive reverse inductor
currents when V
OUT
is sinking current. The negative
current-limit threshold is set to approximately 110% of
the positive current limit, and tracks the positive current
limit when ILIM is adjusted. The current-limit threshold
can be adjusted with an external resistor (R
ILIM
) at ILIM.
A precision 5μA pullup current source at ILIM sets a
voltage drop on this resistor, adjusting the current-limit
threshold from <50mV to >200mV. In the adjustable
mode, the current-limit threshold voltage is precisely
1/10th the voltage seen at ILIM.
Therefore, choose R
ILIM
equal to 2k
/mV of the cur-
rent-limit threshold. The threshold defaults to 100mV
when ILIM is connected to VL. The logic threshold for
switchover to the 100mV default value is approximately
V
L
- 1V. The adjustable current limit can accommodate
various MOSFETs. A capacitor in parallel with R
ILIM
can
provide a variable soft-start function.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by LX and PGND. The IC must
be mounted close to the low-side MOSFET with short,
direct traces making a Kelvin-sense connection to the
source and drain terminals. See the
PC Board Layout
section.
Voltage Positioning
The quick-PWM control architecture responds virtually
instantaneously to transient load changes and elimi-
nates the control loop delay of conventional PWM con-
trollers. As a result, a large portion of the voltage
deviation during a step load change is from the equiva-
lent series resistance (ESR) of the output capacitors.
For DDR termination applications, the maximum
allowed voltage deviation is ±40mV for any output load
transition from sourcing current to sinking current.
Passive voltage positioning adjusts the converter
’
s out-
put voltage based on its load current to optimize tran-
sient response and minimize the required output
capacitance. Voltage positioning is implemented by
connecting a 2m
resistor as shown in Figure 1.
MOSFET Drivers
The DH and DL drivers are optimized for driving mod-
erate-size, high-side and larger, low-side power
MOSFETs and are optimized for 2.5V and 5V input volt-
ages. The drivers are sized to drive MOSFETs that can
deliver up to 25A output current. An adaptive dead-
time circuit monitors the DL output and prevents the
POK
V+
DDR
EN/HSD
REF
GND
ILIM
VTT
VTTR
PGND
VL
BST
DH
LX
DL
FSEL
R
BST
MAX1917
Figure 2. Increasing the On Time of the High-Side MOSFET
POK
V+
DDR
EN/HSD
REF
GND
ILIM
VTT
VTTR
PGND
VL
BST
DH
LX
DL
FSEL
4 x 270
μ
F
2V
V
OUT
V
IN
VTTR
R
DRP
2m
MAX1917
Figure 1. Using a Resistor for Voltage Positioning