M
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
______________________________________________________________________________________
17
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than or
equal to I
LOAD(MAX)
. To protect against this condition,
design the circuit to tolerate:
I
LOAD
= I
LIMIT(HIGH)
+ (LIR / 2) (I
LOAD
(MAX))
where I
LIMIT(HIGH)
is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. If short-circuit
protection without overload protection is enough, a nor-
mal I
LOAD
value can be used for calculating compo-
nent stresses.
Control IC Power Dissipation
MAX1917 has on-chip MOSFETs drivers (DH and DL)
that dissipate the power loss due to driving the external
MOSFETs. Power dissipation due to a MOSFET driver is
given by:
where Q
GH
and Q
GL
are the total gate charge of the
high-side and low-side MOSFETs, respectively. Select
the switching frequency and V+ correctly to ensure the
power dissipation does not exceed the package power
dissipation requirement.
Applications Information
PC Board Layout
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention. If
possible, mount all of the power components on the top
side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
2) Connect GND and PGND together as close to the
IC as possible.
3) Keep the power traces and load connections short.
This practice is essential for high efficiency. The
use of thick copper PC boards (2oz vs. 1oz) can
enhance full-load efficiency by 1% or more.
Correctly routing PC board traces is a difficult task
that must be approached in terms of fractions of
centimeters, where a single m
of excess trace
resistance causes a measurable efficiency penalty.
4) LX and PGND connections to Q2 for current limiting
must be made using Kelvin-sense connections in
order to guarantee the current-limit accuracy. With
8-pin SO MOSFETs, this is best done by routing
power to the MOSFETs from outside using the top
copper layer, while tying in PGND and LX inside
(underneath) the 8-pin SO package.
5) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
6) Ensure that the VTT feedback connection to C
OUT
is short and direct. In some cases, it may be desir-
able to deliberately introduce some trace length
(droop resistance) between the FB inductor node
and the output filter capacitor.
7) VTT feedback sense point should also be as close
as possible to the load connection.
8) Route high-speed switching nodes away from sen-
sitive analog nodes (DDR, EN/HSD, REF, ILIM).
9) Make all pin-strap control input connections (ILIM,
etc.) to GND or VL close to the chip, and do not
connect to PGND.
Chip Information
TRANSISTOR COUNT: 2708
PROCESS: BiCMOS
P
V
f
Q
(
Q
I
DR
S
GH
GL
VTTR
=
+
(
)
×
×
+
)
+
(
)