M
Multichemistry Battery Charger with Automatic
System Power Selector
24
______________________________________________________________________________________
capability is the same for both the low-side and high-
side switches. This is consistent with the variable duty
factor that occurs in the notebook computer environ-
ment where the battery voltage changes over a wide
range. An adaptive dead-time circuit monitors the DLO
output and prevents the high-side FET from turning on
until DLO is fully off. There must be a low-resistance,
low-inductance path from the DLO driver to the MOS-
FET gate for the adaptive dead-time circuit to work
properly. Otherwise, the sense circuitry in the MAX1909
interprets the MOSFET gate as
“
off
”
while there is still
charge left on the gate. Use very short, wide traces
measuring 10 squares to 20 squares or less (1.25mm to
2.5mm wide if the MOSFET is 25mm from the device).
Unlike the DLO output, the DHI output uses a fixed-
delay 50ns time to prevent the low-side FET from turn-
ing on until DHI is fully off. The same layout
considerations should be used for routing the DHI sig-
nal to the high-side FET.
Since the transition time for a P-channel switch can be
much longer than an N-channel switch, the dead time
prior to the high-side PMOS turning on is more pro-
nounced than in other synchronous step-down regula-
tors, which use high-side N-channel switches. On the
high-to-low transition, the voltage on the inductor
’
s
“
switched
”
terminal flies below ground until the low-side
switch turns on. A similar dead-time spike occurs on
the opposite low-to-high transition. Depending upon the
magnitude of the load current, these spikes usually
have a minor impact on efficiency.
The high-side driver (DHI) swings from SRC to 5V
below SRC and typically sources 0.9A and sinks 0.5A
from the gate of the P-channel FET. The internal pull-
down transistors that drive DHI high are robust, with a
2.0
(typ) on-resistance.
The low-side driver (DLO) swings from DLOV to ground
and typically sources 0.5A and sinks 0.9A from the gate
of the N-channel FET. The internal pulldown transistors
that drive DLO low are robust, with a 1.0
(typ) on-
resistance. This helps prevent DLO from being pulled
up when the high-side switch turns on, due to capaci-
tive coupling from the drain to the gate of the low-side
MOSFET. This places some restrictions on the FETs
that can be used. Using a low-side FET with smaller
gate-to-drain capacitance can prevent these problems.
FREQUENCY (Hz)
M
100k
10M
1k
10
-20
0
20
40
60
100
80
-40
-45
0
-90
0.1
MAG
PHASE
P
Figure 10. CCS Loop Response
REFERENCE QTY
DESCRIPTION
C1, C4
2
22μF
±
20%, 35V E-size low-ESR
tantalum capacitors
AVX TPSE226M035R0300
Kemet T495X226M035AS
1μF
±
10%, 25V, X7R ceramic capacitors
(1206)
Murata GRM31MR71E105K
Taiyo Yuden TMK316BJ105KL
TDK C3216X7R1E105K
0.01μF
±
10%, 25V, X7R ceramic
capacitors (0402)
Murata GRP155R71E103K
TDK C1005X7R1E103K
0.1μF
±
10%, 25V, X7R ceramic
capacitors (0603)
Murata GRM188R71E104K
TDK C1608X7R1E104K
1μF
±
10%, 6.3V, X5R ceramic
capacitors (0603)
Murata GRM188R60J105K
Taiyo Yuden JMK107BJ105KA
TDK C1608X5R1A105K
Schottky diode, 0.5A, 30V SOD-123
Diodes Inc. B0530W
General Semiconductor MBR0530
ON Semiconductor MBR0530
C5, C15
2
C9, C10
2
C11, C14,
C17
3
C12, C13,
C16
3
D4
1
D5
1
25V ±1% zener diode
CMDZ5253B
L1
1
10μH, 4.4A inductor
Sumida CDRH104R-100NC
TOKO 919AS-100M
Table 2. Recommended Components