參數(shù)資料
型號: MAX1854
廠商: Maxim Integrated Products, Inc.
英文描述: High-Speed, Adjustable, Synchronous Step-Down Controllers with Integrated Voltage Positioning
中文描述: 高速、數(shù)字可調(diào)、同步降壓型控制器,集成電壓定位電路
文件頁數(shù): 23/33頁
文件大?。?/td> 840K
代理商: MAX1854
M
High-Speed, Adjustable, Synchronous Step-Down
Controllers with Integrated Voltage Positioning
______________________________________________________________________________________
23
When using low-capacity filter capacitors, such as
ceramic or polymer types, capacitor size is usually
determined by the capacity needed to prevent V
SAG,
and V
SOAR
from causing problems during load tran-
sients. Generally, once enough capacitance is added
to meet the overshoot requirement, undershoot at the
rising load edge is no longer a problem (see the V
SAG
equation in the
Design Procedure)
. The amount of over-
shoot due to stored inductor energy can be calculated
as:
V
SOAR
(L
×
I
PEAK
2
) / (2
×
C
OUT
×
V
OUT
)
where I
PEAK
is the peak inductor current.
Output Capacitor Stability Considerations
Stability is determined by the value of the ESR zero rel-
ative to the switching frequency. The boundary of insta-
bility is given by the following equation:
ESR
=
SW
/
π
where:
ESR
= 1 / (2
× π ×
R
ESR
×
C
OUT
)
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP
capacitors in widespread use at the time of this publi-
cation have typical ESR zero frequencies below 30kHz.
In the standard application used for inductor selection,
the ESR needed to support a 50mVp-p ripple is
50mV/(18A
×
0.3) = 9.3m
. Five 220μF/2.5V Panasonic
SP capacitors in parallel provide 3m
(max) ESR. Their
typical combined ESR results in a zero at 48kHz.
Don
t put high-value ceramic capacitors directly across
the output without taking precautions to ensure stability.
Ceramic capacitors have a high ESR zero frequency
and may cause erratic, unstable operation. However,
it
s easy to add enough series resistance by placing
the capacitors a couple of inches downstream from the
junction of the inductor and FB pin.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feed-
back loop instability.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there isn
t enough volt-
age ramp in the output voltage signal. This
fools
the
error comparator into triggering a new cycle immedi-
ately after the minimum off-time period has expired.
Double-pulsing is more annoying than harmful, result-
ing in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability, which is caused by insufficient ESR.
Loop instability can result in oscillations at the output
after line or load perturbations that can cause the out-
put voltage to rise above or fall below the tolerance
limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Don
t
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple-current
requirement (I
RMS
) imposed by the switching currents
defined by the following equation:
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resistance to inrush surge currents typical of systems
with a mechanical switch or connector in series with the
input. If the MAX1716/MAX1854/MAX1855 are operated
as the second stage of a two-stage power-conversion
system, tantalum input capacitors are acceptable. In
either configuration, choose an input capacitor that
exhibits <+10
°
C temperature rise at the RMS input cur-
rent for optimal circuit longevity.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>18A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
For maximum efficiency, choose a high-side MOSFET
that has conduction losses equal to the switching loss-
es at the average input voltage (3 Li+ cells = 11V, 4 Li+
cells = 14V). Check to ensure that conduction losses
plus switching losses don
t exceed the package ratings
or violate the overall thermal budget at the maximum
and minimum input voltages.
Choose a low-side MOSFET that has the lowest possi-
ble on-resistance (R
DS(ON)
), comes in a moderate-
sized package (i.e., one or two SO-8s, DPAK or
D
2
PAK), and is reasonably priced. Make sure that the
DL gate driver can supply sufficient current to support
the gate charge and the current injected into the para-
sitic gate-to-drain capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction prob-
lems may occur.
I
I
V
V
V
V
RMS
LOAD
OUT
OUT
=
+
+
(
)
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