參數(shù)資料
型號: MAX1799AEUP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Replaced by TMS320C6727B : Digital Signal Processors 325-CPGA 0 to 70
中文描述: FIVE OUTPUT, ADJUSTABLE POSITIVE LDO REGULATOR, PDSO20
封裝: 4.40 MM, MO-153, TSSOP-20
文件頁數(shù): 4/20頁
文件大?。?/td> 642K
代理商: MAX1799AEUP
M
CDMA Cellular/PCS System
Power Supplies
4
_______________________________________________________________________________________
ns
50
t
SP
Maximum Pulse Width of Spikes
that Must Be Suppressed by the
Input Filter of Both SDA and
SCK Signals
ns
100
t
SU_DAT
Data Setup Time
CONDITIONS
μs
0
t
HD_DAT
Data Hold Time
μs
1.3
t
BUF
Bus-Free Time Between START
and STOP
kHz
400
SCK
Clock Frequency
μs
0.6
t
SU_STA
Setup Time Repeated START
Condition
μs
0.6
t
HD_STA
Hold Time Repeated START
Condition
μs
μs
1.3
0.6
t
LOW
t
HIGH
SCK Low Period
SCK High Period
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Setup Time for STOP Condition
SPI TIMING (MAX1798/MAX1798A)
t
SU_STO
0.6
μs
SCLK Clock Frequency
SCLK Low Period
SCLK High Period
Data Hold Time
Data Setup Time
f
SCLK
t
cl
t
ch
t
HD_DAT
t
SU_DAT
2
MHz
ns
ns
ns
ns
125
125
0
125
CS
Assertion to SCLK Rising
Edge Setup Time
t
CSS
200
ns
CS
Deassertion to SCLK Rising
Edge Setup Time
t
CS1
200
ns
SCLK Rising Edge to
CS
Deassertion
t
CSH
200
ns
SCLK Rising Edge to
CS
Assertion
t
CSO
200
ns
CS
High Period
t
CSW
300
ns
I
2
C (SMB) TIMING (MAX1799/MAX1799A)
ELECTRICAL CHARACTERISTICS (continued)
(V
IN1
= V
IN2/3
= V
IN4/5
= V
SCLK (SCK)
= V
DIN (SDA)
= V
CS
(AS)
= V
OFF
= 3.6V;
ON
= GND = PGND = 0; RSO, ONO, DR1, DR2 =
open; BP bypassed with 0.01μF, OUT1 bypassed with 4.7μF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2μF; OUT1
5 set to 2.98V,
T
A
= 0
°
C to +85
°
C
, unless otherwise noted. Typical values are at T
A
= +25
°
C.)
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