參數(shù)資料
型號(hào)： MAX1799AEUP
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Replaced by TMS320C6727B : Digital Signal Processors 325-CPGA 0 to 70
中文描述： FIVE OUTPUT, ADJUSTABLE POSITIVE LDO REGULATOR, PDSO20
封裝： 4.40 MM, MO-153, TSSOP-20
文件頁(yè)數(shù)： 13/20頁(yè)
文件大?。?/td> 642K
代理商： MAX1799AEUP
M
CDMA Cellular/PCS System
Power Supplies
______________________________________________________________________________________
13
watchdog timers time out, the shutdown timer is reset.
The shutdown timer requires continuous low
RSO
signal
and continuous nontriggered watchdog timer to shut
down the regulators.
ON
and
OFF
Logic
See Figure 3. The MAX1798/MAX1798A/MAX1799/
MAX1799A power up when V
IN1
is greater than 2.5V
and
ON
is low (
ON
button is pressed down momentari-
ly). When
ON
returns high, the device remains on. It
turns on OUT1 and the serial interface port. Once
OUT1 is in regulation,
RSO
stays low an additional
140ms (min). At this time, OUT1 is on and set to 2.98V,
while OUT2
–
5 are disabled and set to 2.98V. To stay
on, the
OFF
pin must be in a high state within 35ms
(min) or the device will shut down and can only be
turned on by pressing the
ON
button. While
ON
is held
low, the status of
OFF
is irrelevant and OUT1 and the
serial port are on.
After initial power-up, the logic level of ONO follows the
logic level of
ON
but is level-shifted to OUT1 high volt-
age. This signal can be used to interrupt the system
controller, which can subsequently manage an orderly
shutdown through the serial port by turning off OUT1.
140ms min
140ms min
35ms max
35ms max
52ms typ
35ms max
10
μ
s min
PULSED HIGH
OR CONTINUOUS HIGH
ON
(INPUT)
OUT1
RSO
(OUTPUT)
OFF
(INPUT)
ONO
(OUTPUT)
Figure 3. Push-On/Push-Off Startup and Shutdown Timing Diagram
SCL
A
B
C
D
E
F
G
H
I
J
K
SDA
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
L
M
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
Figure 2. I
2
C-Compatible Serial-Interface Timing Diagram
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