參數(shù)資料
型號(hào): MAX1762
廠商: Maxim Integrated Products, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Replaced by TMS320VC5506 : Digital Signal Processor 100-LQFP
中文描述: 高效率、10引腳µMAX、降壓型控制器,用于筆記本電腦
文件頁數(shù): 16/20頁
文件大小: 391K
代理商: MAX1762
M
High-Efficiency, 10-Pin μMAX, Step-Down
Controllers for Notebooks
16
______________________________________________________________________________________
fools
the error comparator into triggering a new cycle
immediately after the 500ns minimum off-time period has
expired. Double pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability, which is caused by insufficient ESR. Loop
instability can result in oscillations at the output after line
or load perturbations that can cause the output voltage
to fall below the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient (refer to the
MAX1762/MAX1791 EV kit manual) and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Don
t
allow more than one cycle of ringing after the initial
step-response under- or overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple-current require-
ment (I
RMS
) imposed by the switching currents.
Nontantalum chemistries (ceramic or OS-CON
) are pre-
ferred due to their resilience to power-up surge currents:
Power MOSFET Selection
DC bias and output power considerations dominate the
selection of the power MOSFETs used with the
MAX1762/MAX1791. Take care not to exceed the
device
s maximum voltage ratings. In general, both
switches are exposed to the supply voltage, so select
MOSFETs with V
DS
(max) greater than VP (max). Gate
drives to the N-channel and P-channel MOSFETs are
not symmetrical. The N-channel device is driven from
ground to the logic supply VL, while the P-channel
device is driven from VP to ground. The maximum rat-
ing for V
GS
for the N-channel device is usually not an
issue; however, V
GS
(max) for the P-channel must be at
least VP (max). Since V
GS
(max) is usually lower than
V
DS
(max), gate drive constraints often dictate the
required P-channel breakdown rating.
For moderate input-to-output differentials, the high-side
MOSFET (Q1) can be sized smaller than the low-side
MOSFET (Q2) without compromising efficiency. The
high-side switch operates at a very low duty cycle
under these conditions, so most conduction losses
occur in Q2. For maximum efficiency, choose a high-
side MOSFET (Q1) that has conduction losses (I
2
R x
Duty Cycle) equal to the switching losses (CV
VP
2
f).
Make sure that the conduction losses at the minimum
input voltage do not exceed the package thermal limits
or violate the overall thermal budget. Conduction losses
plus switching losses at the maximum input voltage
should not exceed the package ratings or violate the
overall thermal budget (see
MOSFET Power Dis-
sipation
).
In addition to efficiency considerations, the selection of
the R
DS(ON)
of the low-side MOSFET must account for
the regulator
s required current limit. Choose a MOS-
FET that has a low enough resistance over the operat-
ing temperature range such that the device will not
enter current limit during normal operation (see
Determining Current Limit
). Conversely, ultra-low
R
DS(ON)
devices may set the current limit too high and
may result in only incremental improvements in efficien-
cy. Some large N-channel FETs also have substantial
interelectrode capacitance. Verify that the MAX1762/
MAX1791 DL driver can hold the gate off when the high
side switch turns on. Cross-conduction problems can
occur when the high-side switch turns on due to cou-
pling through the N-channel
s parasitic drain-to-gate
capacitance.
The MAX1762/MAX1791 have adaptive dead-time cir-
cuitry that prevents the high-side and low-side
MOSFETs from conducting at the same time (see
MOS-
FET Gate Drivers
). Even with this protection, it is still
possible for delays internal to the MOSFET to prevent
one MOSFET from turning off while the other is turned
on. The maximum mismatch time that can be tolerated
is 60ns. Select devices that have low turn-off times, and
make sure that NFET(t
D
(off,max)) - PFET(t
D
(on,min)) <
60ns, and PFET(t
D
(off,max)) - NFET(t
D
(on,min)) < 60ns.
Failure to do so may result in efficiency-killing shoot-
through currents.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation (PD) due to resistance occurs at min-
imum battery voltage:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltage. However,
the R
DS(ON)
required to stay within package power-dis-
sipation limits often limits how small the MOSFET can
be. Again, the optimum occurs when the switching (AC)
losses equal the conduction (R
DS(ON)
) losses. High-
PD(Q1 resistance)
V
V
I
R
OUT
VP(MIN)
LOAD
DS(ON)
2
=
×
×
I
V
(V
-V
)
RMS
LOAD
I
OUT
VP
OUT
VP
I
=
OS-CON is a trademark of Sanyo.
相關(guān)PDF資料
PDF描述
MAX1762-MAX1791 High-Efficiency, 10-Pin レMAX, Step-Down Controllers for Notebooks
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