參數(shù)資料
型號(hào)： MAX1737EVKIT
廠商： Maxim Integrated Products, Inc.
英文描述： MAX1737 Evaluation Kit
中文描述： MAX1737評(píng)估板
文件頁(yè)數(shù)： 17/18頁(yè)
文件大?。?/td> 234K
代理商： MAX1737EVKIT
M
Stand-Alone Switch-Mode
Lithium-Ion Battery-Charger Controller
______________________________________________________________________________________
17
For the high-side switch, the worst-case power dissipa-
tion due to on-resistance occurs at the minimum source
voltage V
DCIN(MIN)
and the maximum battery voltage
V
BATT(MAX)
, and can be approximated by the equation:
The transition loss can be approximated by the equation:
where t
TR
is the MOSFET transition time. So the total
power dissipation of the high-side switch is P
TOT
= P
R
+ P
T
.
The worst-case synchronous-rectifier power occurs at
the minimum battery voltage V
BATT(MIN)
and the maxi-
mum source voltage V
DC(MAX)
, and can be approxi-
mated by:
There is a brief dead time where both the high-side
switch and synchronous rectifier are off. This prevents
crowbar currents that flow directly from the source volt-
age to ground. During the dead time, the inductor cur-
rent will turn on the synchronous-rectifier MOSFET body
diode, which may degrade efficiency. To prevent this,
connect a Schottky rectifier across the drain source of
the synchronous rectifier to stop the body diode from
conducting. The Schottky rectifier may be omitted, typi-
cally degrading the efficiency by approximately 1% to
2%, causing a corresponding increase in the low-side
synchronous-rectifier power dissipation.
VL and REF Bypassing
The MAX1737 uses an internal linear regulator to drop
the input voltage down to 5.4V, which powers the inter-
nal circuitry. The output of the linear regulator is the VL
pin. The internal linear regulator may also be used to
power external circuitry as long as the maximum current
and power dissipation of the linear regulator are not
exceeded. The synchronous-rectifier MOSFET gate dri-
ver (DLO) is powered from VLO. An internal 12
resistor
from VL to VLO provides the DC current to power the
gate driver. Bypass VLO to PGND with a 0.1μF or
greater capacitor.
A 4.7μF bypass capacitor is required at VL to ensure
that the regulator is stable. A 1μF bypass capacitor is
also required between REF and GND to ensure that the
internal 4.2V reference is stable. In both cases use a
low-ESR ceramic capacitor.
Chip Information
TRANSISTOR COUNT: 5978
P
V
V
V
R
I
DL
DCIN MAX
(
BATT MIN
DCIN MAX
(
DS ON
(
CHG
≈
×
×
)
(
)
)
)
2
P
V
I
f
t
T
DCIN
CHG
TR
≈
×
×
×
3
P
V
V
R
I
R
BATT MAX
DCIN MIN
DS ON
(
CHG
≈
×
×
(
)
(
)
)
2
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