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| 型號(hào)： | MAX1737EVKIT |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | MAX1737 Evaluation Kit |
| 中文描述： | MAX1737評(píng)估板 |
| 文件頁(yè)數(shù)： | 15/18頁(yè) |
| 文件大?。?/td> | 234K |
| 代理商： | MAX1737EVKIT |
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M
Stand-Alone Switch-Mode
Lithium-Ion Battery-Charger Controller
_______________________________________________________________________________________
15
Design Procedure
Setting the Battery Regulation Voltage
VADJ sets the per-cell voltage limit. To set the VADJ
voltage, use a resistor-divider from REF to GND. A
GND-to-VREF change at VADJ results in a ±5% change
in the battery limit voltage. Since the full VADJ range
results in only a 10% change on the battery regulation
voltage, the resistor-divider’s accuracy need not be as
high as the output voltage accuracy. Using 1% resis-
tors for the voltage-dividers results in no more than
0.1% degradation in output voltage accuracy. VADJ is
internally buffered so that high-value resistors can be
used. Set V
VADJ
by choosing a value less than 100k
for R8 and R9 (Figure 1) from VADJ to GND. The per-
cell battery termination voltage is a function of the bat-
tery chemistry and construction; thus, consult the
battery manufacturer to determine this voltage. Once
the per-cell voltage limit battery regulation voltage is
determined, the VADJ voltage is calculated by the
equation:
CELL is the programming input for selecting cell count
N. Table 2 shows how CELL is connected to charge
one to four cells.
Setting the Charging Current Limit
A resistor-divider from REF to GND sets the voltage at
ISETOUT (V
ISETOUT
). This voltage determines the
charging current during the current-regulation fast-
charge mode. The full-scale charging current (I
FSI
) is
set by the current-sense resistor (R18, Figure 1)
between CS and BATT. The full-scale current is I
FSI
=
0.2V / R18.
The charging current I
CHG
is therefore:
In choosing the current-sense resistor, note that the drop
across this resistor causes further power loss, reducing
efficiency. However, too low a value may degrade the
accuracy of the charging current.
Setting the Input Current Limit
A resistor-divider from REF to GND can set the voltage
at ISETIN (V
ISETIN
). This sets the maximum source cur-
rent allowed at any time during charging. The source
current (I
FSS
) is set by the current-sense resistor (R12,
Figure 1) between CSSP and CSSN. The full-scale
source current is I
FSS
= 0.1V / R12.
The input current limit (I
IN
) is therefore:
Set ISETIN to REF to get the full-scale current limit.
Short CSSP and CSSN to DCIN if the input source cur-
rent limit is not used.
In choosing the current-sense resistor, note that the
drop across this resistor causes further power loss,
reducing efficiency. However, too low a resistor value
may degrade input current limit accuracy.
Inductor Selection
The inductor value may be changed to achieve more or
less ripple current. The higher the inductance, the
lower the ripple current will be; however, as the physi-
cal size is kept the same, higher inductance typically
will result in higher series resistance and lower satura-
tion current. A good trade-off is to choose the inductor
so that the ripple current is approximately 30% to 50%
of the DC average charging current. The ratio of ripple
current to DC charging current (LIR) can be used to
calculate the optimal inductor value:
where f is the switching frequency (300kHz).
The peak inductor current is given by:
Capacitor Selection
The input capacitor absorbs the switching current from
the charger input and prevents that current from circu-
lating through the source, typically an AC wall cube.
Thus, the input capacitor must be able to handle the
input RMS current. Typically, at high charging currents,
the converter will operate in continuous conduction (the
inductor current does not go to 0). In this case, the
RMS current of the input capacitor may be approximat-
ed by the equation:
where I
CIN
= the input capacitor RMS current, D =
PWM converter duty ratio (typically V
BATT
/ V
DCIN
), and
I
CHG
= battery charging current.
The maximum RMS input current occurs at 50%
duty cycle, so the worst-case input ripple current is
I
I
CIN
CHG
D D
2
≈
I
I
LIR
2
PEAK
CHG
=
+
1
L
V
V
V
V
f
I
LIR
BATT
DCIN MAX
×
)
BATT
×
DCIN MAX
(
CHG
=
×
(
)
(
)
I
I
V
V
IN
FSS
ISETIN
REF
=
I
I
V
V
CHG
FSI
ISETOUT
REF
=
V
9.5 V
N
(9.0 V
)
ADJ
BATTR
REF
=
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