參數(shù)資料
型號: MAX1717
廠商: Maxim Integrated Products, Inc.
元件分類: 數(shù)字信號處理
英文描述: Replaced by TMS320VC5506 : Digital Signal Processors 132-BQFP
中文描述: 動態(tài)可調(diào)、同步降壓型控制器,用于筆記本CPU
文件頁數(shù): 30/32頁
文件大?。?/td> 501K
代理商: MAX1717
M
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
30
______________________________________________________________________________________
The two-stage approach allows flexible placement due
to smaller circuit size and reduced local power dissipa-
tion. The power supply can be placed closer to the
CPU for better regulation and lower I
2
R losses from PC
board traces. Although the two-stage design has worse
transient response than the single stage, this can be
offset by the use of a voltage-positioned converter.
Ceramic Output Capacitor
Applications
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR and are noncom-
bustible, relatively small, and nonpolarized. They are
also expensive and brittle, and their ultra-low ESR char-
acteristic can result in excessively high ESR zero fre-
quencies (affecting stability in nonvoltage-positioned
circuits). In addition, their relatively low capacitance
value can cause output overshoot when going abruptly
from full-load to no-load conditions, unless the inductor
value can be made small (high switching frequency), or
there are some bulk tantalum or electrolytic capacitors
in parallel to absorb the stored energy in the inductor.
In some cases, there may be no room for electrolytics,
creating a need for a DC-DC design that uses nothing
but ceramics.
The MAX1717 can take full advantage of the small size
and low ESR of ceramic output capacitors in a voltage-
positioned circuit. The addition of the positioning resistor
increases the ripple at FB, lowering the effective ESR
zero frequency of the ceramic output capacitor.
Output overshoot (V
SOAR
) determines the minimum
output capacitance requirement (see
Output Capacitor
Selection
). Often the switching frequency is increased to
550kHz or 1000kHz, and the inductor value is reduced to
minimize the energy transferred from inductor to capacitor
during load-step recovery. The efficiency penalty for
operating at 550kHz is about 2% to 3% and about 5% at
1000kHz when compared to the 300kHz voltage-
positioned circuit, primarily due to the high-side MOSFET
switching losses.
Table 1 and the
Typical Operating Characteristics
include two circuits using ceramic capacitors with
1000kHz switching frequencies. The efficiency of the
+5V input circuit (circuit 4) is substantially higher than
circuit 5, which accommodates the full battery voltage
range. Circuit 4 is an excellent choice for two-stage
conversion applications if the goal is to minimize size
and power dissipation near the CPU.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 12). If possible, mount all of the power compo-
nents on the top side of the board with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
2) All analog grounding is done to a separate solid cop-
per plane, which connects to the MAX1717 at the
GND pin. This includes the V
CC
, REF, and CC
capacitors, the TIME resistor, as well as any other
resistor-dividers.
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
4) LX and GND connections to Q2 for current limiting
must be made using Kelvin sense connections to
guarantee the current-limit accuracy. With SO-8
MOSFETs, this is best done by routing power to the
MOSFETs from outside using the top copper layer,
while connecting GND and LX inside (underneath)
the SO-8 package.
5) When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-side
MOSFET or between the inductor and the output filter
capacitor.
6) Ensure the FB connection to the output is short and
direct. In voltage-positioned circuits, the FB connection
is at the junction of the inductor and the positioning
resistor.
7) Route high-speed switching nodes away from sensitive
analog areas (CC, REF, ILIM). Make all pin-strap
control input connections (SKP/
SDN
, ILIM, etc.) to ana-
log ground or V
CC
rather than power ground or V
DD
.
Layout Procedure
1) Place the power components first, with ground termi-
nals adjacent (Q2 source, CIN-, COUT-, D1 anode).
If possible, make all these connections on the top
layer with wide, copper-filled areas.
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MAX1717BEEG+T 功能描述:DC/DC 開關(guān)控制器 Adj Synchronous Step-Down RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK
MAX1717BEEG-T 功能描述:DC/DC 開關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK