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參數(shù)資料
| 型號： | MAX149BMJP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | MAX149BMJP |
M
+2.7V to +5.25V, Low-Power, 8-Channel,
S erial 10-Bit ADCs
______________________________________________________________________________________
15
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7μF compen-
sation capacitor when the capacitor is initially fully
discharged. From fast power-down, start-up time can be
eliminated by using low-leakage capacitors that do not
discharge more than 1/2LSB while shut down. In power-
down, leakage currents at VREF cause droop on the ref-
erence bypass capacitor. Figures 12a and 12b show
the various power-down sequences in both external and
internal clock modes.
SCLK
DIN
DOUT
CS
S
CONTROL BYTE 0
CONTROL BYTE 1
S
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
SSTRB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONTROL BYTE 2
S
1
8
1
15
15
8
1
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
CS
SCLK
DIN
DOUT
S
1
8
16
1
8
16
CONTROL BYTE 0
CONTROL BYTE 1
S
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
B9 B8 B7 B6
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
POWERED UP
HARDWARE
POWER-
DOWN
POWERED UP
POWERED UP
10 + 2 DATA BITS
10 + 2 DATA BITS
INVALID
DATA
VALID
DATA
EXTERNAL
EXTERNAL
S X X X X X 1 1
S
0 0
X
X
X
X
X
X X X X X
S
1 1
SOFTWARE
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
SETS SOFTWARE
POWER-DOWN
Figure 12a. Timing Diagram Power-Down Modes, External Clock
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