參數資料
型號: MAX149BMJP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
中文描述: 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20
封裝: CERDIP-20
文件頁數: 10/24頁
文件大?。?/td> 221K
代理商: MAX149BMJP
M
+2.7V to +5.25V, Low-Power, 8-Channel,
S erial 10-Bit ADCs
10
______________________________________________________________________________________
How to S tart a Conversion
Start a conversion by clocking a control byte into DIN.
With
CS
low, each rising edge on SCLK clocks a bit from
DIN into the MAX148/MAX149’s internal shift register.
After
CS
falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX148/MAX149 are compatible with SPI/
QSPI and MICROWIRE devices. For SPI, select the cor-
rect clock polarity and sampling edge in the SPI control
registers: set CPOL = 0 and CPHA = 0. MICROWIRE,
SPI, and QSPI all transmit a byte and receive a byte at
the same time. Using the Typical Operating Circuit, the
simplest software interface requires only three 8-bit
transfers to perform a conversion (one 8-bit transfer to
configure the ADC, and two more 8-bit transfers to clock
out the conversion result). See Figure 20 for MAX148/
MAX149 QSPI connections.
BIT
NAME
DESCRIPTION
7(MSB)
START
The first logic “1” bit after
CS
goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF/2 to +VREF/2.
2
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
1
0(LSB)
PD1
PD0
Selects clock and power-down modes.
PD1
PD0
0
0
0
1
1
0
1
1
Mode
Full power-down
Fast power-down (MAX149 only)
Internal clock mode
External clock mode
Table 1. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
SEL2
0
SEL1
0
SEL0
0
CH0
+
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
0
0
+
0
0
1
+
1
0
1
+
0
1
0
+
1
1
0
+
0
1
1
+
1
1
1
+
Table 2. Channel Selection in Single-Ended Mode (SGL/
DIF
= 1)
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