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參數(shù)資料
| 型號(hào)： | MAX1497 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | LED驅(qū)動(dòng)器 |
| 英文描述： | 3.5- and 4.5-Digit. Single-Chip ADCs with LED Drivers and 礐 Interface |
| 中文描述： | 3位半和4位半、單片ADC，帶有LED驅(qū)動(dòng)器和µC接口 |
| 文件頁(yè)數(shù)： | 6/33頁(yè) |
| 文件大?。?/td> | 665K |
| 代理商： | MAX1497 |
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M
3.5- and 4.5-Digit, Single-Chip ADCs with LED
Drivers and μC Interface
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS (Notes 11, 12, Figure 8)
(AV
DD
= DV
DD
= V
DD
= +2.7V to +5.25V, GND = 0, GLED = 0, V
LED
= +2.7V to +5.25V, V
REF+
- V
REF-
= 2.048V (external reference)
C
REF+
= C
REF-
= 0.1μF, C
VNEG
= 0.1μF. Internal clock mode, unless otherwise noted. All specifications are at T
A
= T
MIN
to T
MAX
.
Typical values are at T
A
= +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
f
SCLK
t
CH
t
CL
t
DS
t
DH
t
CSS
t
CSH
t
DO
t
TR
t
DV
CONDITIONS
MIN
0
100
100
50
0
50
0
TYP
MAX
4.2
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Operating Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN to SCLK Setup
DIN to SCLK Hold
CS
Fall to SCLK Rise Setup
SCLK Rise to
CS
Rise Hold
SCLK Fall to DOUT Valid
CS
Rise to DOUT Disable
CS
Fall to DOUT Enable
C
LOAD
= 50pF, Figures 13, 14
C
LOAD
= 50pF, Figures 13, 14
C
LOAD
= 50pF, Figures 13, 14
120
120
120
Note 1:
Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and
offset error.
Note 2:
Offset calibrated. See
OFFSET_CAL1
and OFFSET_CAL2 (MAX1499 only) in the
On-Chip Registers
section.
Note 3:
Offset nulled.
Note 4:
Offset drift error is eliminated by recalibration at the new temperature.
Note 5:
The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
Note 6:
V
AIN
+ or V
AIN
- = -2.2V to +2.2V. V
REF
+ or V
REF
- = -2.2V to +2.2V. All input structures are identical. Production tested on
AIN+ and REF+ only.
Note 7:
Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion
error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2).
Note 8:
CLK and SCLK are disabled.
Note 9:
LED drivers are disabled.
Note 10:
Power-supply currents are measured with all digital inputs at either GND, DV
DD
, or V
DD
and with the device in internal-clock mode.
Note 11:
All input signals are specified with t
RISE
= t
FALL
= 5ns (10% to 90% of DV
DD
) and are timed from a voltage level of 50% of
DV
DD
, unless otherwise noted.
Note 12:
See the serial-interface timing diagrams.
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