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參數(shù)資料
| 型號(hào)： | MAX1478 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 1% Accurate, Digitally Trimmed,Rail-to-Rail Sensor Signal Conditioner |
| 中文描述： | 1%精確度、數(shù)字校準(zhǔn)、滿擺幅傳感器信號(hào)調(diào)理器 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 210K |
| 代理商： | MAX1478 |
a V
DD
of 5V. The output of the Offset DAC is fed into
the output summing junction where it is gained by
approximately 2.3, which increases the resulting out-
put-referred offset correction resolution to 2.8mV.
Both the Offset TC and FSOTC DACs take their refer-
ence from BDRIVE, a temperature-dependent voltage.
A nominal V
BDRIVE
of 2.5V results in a step size of
0.6mV. The Offset TC DAC output is fed into the output
summing junction where it is multiplied by approximate-
ly 2.3, thereby increasing the Offset TC correction
range. The buffered FSOTC DAC output is available at
FSOTC and is connected to ISRC through R
FTC
to cor-
rect FSO TC errors.
Internal Resistors
The MAX1478 contains three internal resistors (R
ISRC
,
R
FTC
, and R
TEMP
) optimized for common silicon PRTs.
R
ISRC
(in conjunction with the FSO DAC) programs the
nominal sensor excitation current. R
FTC
(in conjunction
with the FSOTC DAC) compensates the FSO TC errors.
Both R
ISRC
and R
FTC
have a nominal value of 75k
. If
external resistors are used, R
ISRC
and R
FTC
can be dis-
abled by resetting the appropriate bit (address 07h
reset to zero) in the configuration register (Table 3).
R
TEMP
is a high-tempco resistor with a TC of
+4600ppm/°C and a nominal resistance of 100k
at
+25°C. This resistor can be used with certain sensor
types that require an external temperature sensor.
Internal EEPROM
The MAX1478 has a 128-bit internal EEPROM arranged
as eight 16-bit words. The four uppermost bits for each
register are reserved. The internal EEPROM is used to
store the following (also shown in the memory map in
Table 4):
M
1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner
_______________________________________________________________________________________
7
Figure 3. Bridge Excitation Circuit
V
DD
AA
≈
14I
ISRC
= I
BDRIVE
I = I
ISRC
I
SRC
FSOTC
R
ISRC
BDRIVE
V
DD
R
FTC
EXTERNAL
SENSOR
FSO
DAC
FSOTC
DAC
Table 3. Configuration Register
Input-Referred Offset
Input-Referred Offset (LSB)
0Ah
0Bh
Input-Referred Offset (IRO) Sign Bit
Input-Referred Offset (MSB)
08h
09h
Reserved “0”
Internal Resistor (R
FTC
and R
ISRC
)
Selection
06h
PGA Gain (LSB), A0
Reserved “0”
07h
04h
05h
PGA Gain (MSB), A2
PGA Gain, A1
EEPROM
ADDRESS (hex)
02h
03h
DESCRIPTION
Offset TC Sign Bit, SOTC (+ = 1)
Offset Sign Bit, SOFF (+ = 1)
00h
01h
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