參數(shù)資料
型號(hào)： MAX1478
廠商： Maxim Integrated Products, Inc.
英文描述： 1% Accurate, Digitally Trimmed,Rail-to-Rail Sensor Signal Conditioner
中文描述： 1%精確度、數(shù)字校準(zhǔn)、滿擺幅傳感器信號(hào)調(diào)理器
文件頁數(shù)： 10/20頁
文件大小： 210K
代理商： MAX1478
M
Control Words
After receiving the INIT SEQUENCE on DIO, the MAX1478
begins latching in 16-bit control words, LSB first (Figure 5).
The first 12 bits (D0–D11) represent the data field. The
last 4 bits of the control word (the MSBs, CM0–CM3)
are the command field. The MAX1478 supports the
commands listed in Table 5.
ERASE EEPROM Command
When an ERASE EEPROM command is issued, all of
the memory locations in the EEPROM are reset to a
logic 0. The data field of the 16-bit word is ignored.
Important: An internal charge pump develops voltages
greater than 20V for EEPROM programming operations.
The EEPROM control logic requires 50ms to erase the
EEPROM. After sending a WRITE or ERASE command,
failure to wait 50ms before issuing another command
may result in data being accidentally written to the
EEPROM. The maximum number of ERASE EEPROM
cycles should not exceed 100.
BEGIN EEPROM WRITE Command
The BEGIN EEPROM WRITE command stores a logic
high at the memory location specified by the lower 7
bits of the data field (A0–A6). The higher bits of the
data field (A7–A11) are ignored (Figure 6). Note that to
write to the internal EEPROM, WE and CS must be high.
1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner
10
______________________________________________________________________________________
Figure 5. Control-Word Timing Diagram
SCLK
DIO
DATA
LSB
MSB
MSB
LSB
LSB
MSB
MSB
LSB
COMMAND
16-BIT CONFIGURATION WORD
D6
D9
D7
D10
D8
D11 CM0 CM2 CM2 CM3
D0
D3
D1
D4
D2
D5
Figure 6. Timing Diagram for WRITE EEPROM Operation
WE
CS
SCLK
DIO
t
MIN
200
μ
s
16 CLK
CYCLES
INIT SEQUENCE
BEGIN
EEPROM
WRITE
END
EEPROM
WRITE
t
WAIT
T
WRITE
n
COMMAND
WORDS
16 CLK
CYCLES
n x 16 CLK
CYCLES
X
1
0
1
A0
D0
A0
A1
D1
A1
CM3
CM3
CM3
0
U
0
Table 5. MAX1478 Commands
FUNCTION
ERASE EEPROM
CM2
0
CM1
0
1h
HEX
CODE
CM3
0
CM0
1
BEGIN EEPROM WRITE at
Address
0
1
2h
0
0
READ EEPROM at Address
Maxim Reserved
0
1
1
0
3h
4h
0
0
1
0
END EEPROM WRITE at
Address
1
0
5h
0
1
WRITE Data to Configuration
Register
0
0
8h
1
0
WRITE Offset DAC
WRITE Offset TC DAC
WRITE FSO DAC
WRITE FSOTC DAC
No Operation
0
0
0
1
0
1
1
1
1
1
0
1
1
0
0
1
1
0
1
1
9h
Ah
Bh
Ch
0h
6h,
7h,
Dh,
Eh,
Fh
1
1
1
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
0
1
Load Register
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