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參數(shù)資料
| 型號(hào)： | MAX1457CCJ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | 0.1%-Accurate Signal Conditioner for Piezoresistive Sensor Compensation |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大小： | 93K |
| 代理商： | MAX1457CCJ |
M
0.1%-Ac c urate S ignal Conditioner
for Piezoresistive S ensor Compensation
4
_______________________________________________________________________________________
______________________________________________________________Pin Desc ription
1
2
3
4
5
28
29
30
31
1
Positive Sensor Input. Input impedance >1M
.
Rail-to-rail input range.
Negative Sensor Input. Input impedance >1M
.
Rail-to-rail input range.
Positive Input of General-Purpose Operational Amplifier
Negative Input of General-Purpose Operational Amplifier
Output of General-Purpose Operational Amplifier. High impedance when MCS is low.
—
4, 16,
22, 32
5
Not internally connected.
7
3
PGA Output Voltage. Connect a 0.1μF capacitor from VOUT to V
SS
. High impedance when
MCS is low.
6
2
Sensor Excitation Current. This pin drives a nominal 0.5mA through the sensor.
12
13
14
15
16
17
18
9
Reference Input to FSO Linearity DAC. Normally tied to VOUT.
FSO Linearity DAC Output Voltage. Connect 0.1μF capacitor from LINDAC to V
SS
.
Negative Power Supply Input
OFFSET TC DAC Output Voltage. Connect a 0.1μF capacitor from OTCDAC to V
SS
.
FSO DAC Output Voltage. Connect a 0.1μF capacitor from FSODAC to V
SS
.
FSO TC DAC Output Voltage. Connect a 0.1μF capacitor from FSOTCDAC to V
SS
.
OFFSET DAC Output Voltage. Connect a 0.1μF capacitor from OFSTDAC to V
SS
.
Serial Input (data from EEPROM), active high. CMOS logic-level input pin through which the
MAX1457’s internal registers are updated with EEPROM coefficients. Disabled when MCS is
low.
11
8
Buffered FSO Linearity DAC Output. Use a resistor (R
LIN
) greater than 100k
, from LINOUT
to ISRC to correct second order FSO nonlinearity errors. Leave unconnected if not
correcting second order FSO nonlinearity errors.
10
7
Buffered Bridge Voltage (the voltage at BDRIVE). Leave unconnected if unused.
9
6
Buffered FSO TC DAC Output. Tie to ISRC with a resistor (R
STC
≥
50k
).
8
Current-Source Reference. Connect a 50k
resistor from ISRC to V
SS
.
INP
INM
AMP+
AMP-
AMPOUT
N.C.
VOUT
BDRIVE
LINDACREF
LINDAC
V
SS
OTCDAC
FSODAC
FSOTCDAC
OFSTDAC
LINOUT
VBBUF
FSOTCOUT
ISRC
10
11
12
13
14
15
19
17
EDO
20
18
Serial Output (data to EEPROM), active high. CMOS logic-level output pin through which
the MAX1457 gives external commands to the EEPROM. Temperature-compensation data
is available through this pin. Becomes high impedance when MCS is low.
CMOS Logic-Level Clock Output for external EEPROM. High impedance when MCS is low.
Chip-Select Output for external EEPROM. CMOS logic-level output pin through which the
MAX1457 enables/disables EEPROM operation. High impedance when MCS is low.
Frequency Output. Internal oscillator output signal. Normally left open.
Frequency Adjust. Connect to V
SS
with a 1.5M
resistor (R
OSC
) to set internal oscillator fre-
quency to 100kHz. Connect a 0.1μF bypass capacitor from FADJ to V
SS
.
Master Chip Select. The MAX1457 is selected when MCS is high. Leave unconnected for
normal operation (internally pulled up to V
DD
with 1M
resistor). External 5k
pull-up may
be required in noisy environments.
Bias Setting Pin. Connect to V
DD
with a 400k
resistor (R
BIAS
). Connect a 0.1μF bypass
capacitor from NBIAS to V
SS
.
Mid-Supply Reference for Analog Circuitry. Connect a 0.1μF capacitor from V
SS
to AGND.
Positive Power-Supply Input. Connect a 0.1μF capacitor from V
DD
to V
SS
.
EDI
21
19
ECLK
22
20
ECS
23
21
FOUT
24
23
FADJ
PIN
FUNCTION
NAME
25
24
MCS
26
25
NBIAS
27
28
26
27
AGND
V
DD
TQFP
SO
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