參數(shù)資料
型號(hào): MAX1444EHJ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference
中文描述: 10-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32
封裝: 5 X 5 MM, TQFP-32
文件頁(yè)數(shù): 5/20頁(yè)
文件大小: 401K
代理商: MAX1444EHJ
M
10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________
5
PARAMETER
SYMBOL
V
HYST
I
IH
I
IL
C
IN
CONDITIONS
MIN
TYP
0.1
MAX
UNITS
V
Input Hysteresis
V
IH
= V
DD
= OV
DD
V
IL
= 0
±
5
±
5
Input Leakage
μA
Input Capacitance
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low
5
pF
V
OL
I
SINK
= 200
μ
A
0.2
V
Output Voltage High
V
OH
I
SOURCE
= 200
μ
A
OV
DD
-
0.2
V
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
I
LEAK
C
OUT
OE
= OV
DD
OE
= OV
DD
±
10
μA
pF
5
V
DD
OV
DD
2.7
1.7
3.0
3.0
19
4
4.5
1
±
0.1
±
0.1
3.6
3.6
27
15
V
V
O p er ati ng f
I N
= 19.91M H z at - 0.5d BFS
S hutd ow n, cl ock i d e, P D =
O E
= OV
D D
O p er ati ng f
I N
= 19.91M H z at - 0.5d BFS
S hutd ow n, cl ock i d e, P D =
O E
= OV
D D
Offset
Gain
mA
μA
mA
μA
mV/V
%/V
Analog Supply Current
I
VDD
Output Supply Current
I
OVDD
20
Power-Supply Rejection
PSRR
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
OE
Fall to Output Enable
OE
Rise to Output Disable
CLK Pulse Width High
CLK Pulse Width Low
Wake-up Time
t
DO
Figure 6 (Note 3)
Figure 5
Figure 5
Figure 6, clock period 25ns
Figure 6, clock period 25ns
(Note 4)
5
10
15
8
ns
ns
ns
ns
ns
μs
t
ENABLE
t
DISABLE
t
CH
t
CL
t
WAKE
12.5
±
3.8
12.5
±
3.8
1.7
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V; OV
DD
= 2.7V; 0.1μF and 1μF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V; REFOUT connected to
REFIN through a 10k
resistor; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 40MHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
+25
°
C guaranteed by production test, < +25
°
C guaranteed by design and characterization; typi-
cal values are at T
A
= +25
°
C.)
Note 1:
SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a +1.024V full-scale
input voltage range.
Note 2:
Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better if referenced to the two-tone envelope.
Note 3:
Digital outputs settle to V
IH
/ V
IL
.
Note 4:
REFIN is driven externally. REFP, COM, and REFN are left floating while powered down.
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