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參數(shù)資料
| 型號： | MAX1429ETN |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications |
| 中文描述： | 1-CH 15-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC56 |
| 封裝： | 8 X 8 MM, 0.8 MM HEIGHT, MO-220, TQFN-56 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 219K |
| 代理商： | MAX1429ETN |
M
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applic ations
14
______________________________________________________________________________________
DC-Coupled Analog Input
While AC-coupling of the input signal is the proper
means for achieving the best dynamic performance, it
is possible to DC-couple the inputs by making use of
the CM potential. Figure 8 shows one method for
accomplishing DC-coupling. The common-mode
potentials at the outputs of amplifiers OA1 and OA2 are
“servoed” by the action of amplifier OA3 to be equal to
the CM potential of the MAX1429. Care must be taken
to ensure that the common-mode loop is stable, and
the R
F
/R
G
ratios of both half circuits must be well
matched to ensure balance.
PC Board Layout Considerations
The performance of any high-dynamic range, high
sample-rate converter may be compromised by poor
PC board layout practices. The MAX1429 is no excep-
tion to the rule, and careful layout techniques must be
observed in order to achieve the specified perfor-
mance. Layout issues are addressed in the following
four categories:
1) Layer assignments
2) Signal routing
3) Grounding
4) Supply routing and bypassing
The MAX1427 evaluation board (MAX1427 EV kit) pro-
vides an excellent frame of reference for board layout,
and the discussion that follows is consistent with the
practices incorporated on the evaluation board.
Layer Assignments
The MAX1427 EV kit is a six-layer board, and the
assignment of layers is discussed in this context. It is
recommended that the ground plane be on a layer
between the signal routing layer and the supply routing
layer(s). This practice prevents coupling from the sup-
ply lines into the signal lines. The MAX1427 EV kit PC
board places the signal lines on the top (component)
layer and the ground plane on layer 2. Any region on
the top layer not devoted to signal routing is filled with
ground plane with vias to layer 2. Layers 3 and 4 are
devoted to supply routing, layer 5 is another ground
plane, and layer 6 is used for the placement of addi-
tional components and for additional signal routing.
A four-layer implementation is also feasible using layer
1 for signal lines, layer 2 as a ground plane, layer 3 for
supply routing, and layer 4 for additional signal routing.
However, care must be taken to make sure that the
clock and signal lines are isolated from each other and
from the supply lines.
S ignal Routing
To preserve good even-order distortion, the signal lines
(those traces feeding the INP and INN inputs) must be
carefully balanced. To accomplish this, the signal traces
should be made as symmetric as possible, meaning that
each of the two signal traces should be the same length
and should see the same parasitic environment. As men-
tioned previously, the signal lines must be isolated from
the supply lines to prevent coupling from the supplies to
the inputs. This is accomplished by making the neces-
sary layer assignments as described in the previous sec-
tion. Additionally, it is crucial that the clock lines be
isolated from the signal lines. On the MAX1427 EV kit,
this is done by routing the clock lines on the bottom layer
(layer 6). The clock lines then connect to the ADC
through vias placed in close proximity to the device. The
clock lines are isolated from the supply lines, by virtue of
the ground plane on layer 5.
The digital output traces should be kept as short as
possible to minimize capacitive loading. The ground
plane on layer 2 beneath these traces should not be
removed so that the digital ground return currents have
an uninterrupted path back to the bypass capacitors.
FROM CM
TOINN
TOINP
OA1
OA2
OA3
R
C2
R
C1
R
G1
R
G2
POSITIVE
INPUT
NEGATIVE
INPUT
R
F1
R
F1
Figure 8. DC-Coupled Analog Input Configuration
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1429ETN+ | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| MAX1429ETN+TD | 制造商:Maxim Integrated Products 功能描述:ADC SGL PIPELINED 100MSPS 15-BIT PARALLEL 56TQFN EP - Tape and Reel |
| MAX1429ETN-D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1429ETN-TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1430ETN+ | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
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