參數(shù)資料
型號(hào): MAX1415CWE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs
中文描述: 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝: 0.300 INCH, MS-013AA, SOP-16
文件頁數(shù): 29/36頁
文件大?。?/td> 669K
代理商: MAX1415CWE
M
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
______________________________________________________________________________________
29
POLL DRDY
OUTPUT
POWER-ON RESET
INITIALIZE
μ
C/
μ
P SERIAL
PORT
WRITE TO THE SETUP REGISTER. SET
SELF-CALIBRATION MODE, GAIN TO 0,
UNIPOLAR MODE, UNBUFFERED MODE.
BEGIN SELF-CALIBRATION/CONVERSION
BY CLEARING FSYNC.
(0x44)
WRITE TO THE COMMUNICATIONS
REGISTER. SET NEXT OPERATION AS
A WRITE TO THE SETUP REGISTER.
(0x10)
WRITE TO THE CLOCK REGISTER. ENABLE
INTERNAL CLOCK. SET CLOCK FREQUENCY
TO 2.4576MHz. SELECT OUTPUT UPDATE
RATE OF 60Hz.
(0xA5)
WRITE TO THE COMMUNICATIONS
REGISTER. SELECT CHANNEL 1 AND SET
NEXT OPERATION AS A WRITE TO THE
CLOCK REGISTER
(0x20)
WRITE TO THE COMMUNICATIONS
REGISTER. SET NEXT OPERATION AS A
READ FROM THE DATA REGISTER.
(0x38)
READ THE DATA REGISTER
(16 BITS)
WRITE TO COMMUNICATIONS REGISTER.
SET NEXT OPERATION AS A READ FROM
THE COMMUNICATIONS REGISTER.
(0x08)
READ THE COMMUNICATIONS REGISTER
(8 BITS)
HARDWARE POLLING
SOFTWARE POLLING
0 (DATA
READY)
0 (DATA
READY)
1 (DATA
NOT
READY)
1 (DATA NOT
READY)
POLL DRDY
BIT
Figure 11. Sample Flow Diagram for Data Conversion
相關(guān)PDF資料
PDF描述
MAX1415ENE 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs
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MAX1415EWE 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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