參數(shù)資料
型號(hào)： MAX1348BETX+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 37/39頁(yè)
文件大?。?/td> 0K
描述： IC ADC/DAC 12BIT W/FIFO 36WQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： ADC，DAC
分辨率（位）： 12 b
采樣率（每秒）： 225k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 36-TQFN 裸露焊盤（6x6）
包裝： 帶卷 (TR)
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
_______________________________________________________________________________________
7
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
65
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
140
CKSEL = 01 (voltage conversion)
9
CKSEL = 10 (voltage conversion),
internal reference on
9
CS or CNVST Rise to EOC Fall—
Internally Clocked
Conversion Time
tDOV
CKSEL = 10 (voltage conversion),
internal reference initially off
80
s
CKSEL = 00, CKSEL = 01 (temp sense)
40
ns
CNVST Pulse Width
tCSW
CKSEL = 01 (voltage conversion)
1.4
s
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 4.75V to 5.25V, external reference VREF = 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD = DVDD = 5V, TA = +25°C. Outputs are unloaded, unless otherwise noted.)
Note 1: Tested at DVDD = AVDD = +5.25V.
Note 2: Offset nulled.
Note 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles, multiplied by the
clock period.
Note 4: See Table 5 for reference-mode details.
Note 5: Not production tested. Guaranteed by design.
Note 6: See the
ADC/DAC References section.
Note 7: Fast automated test, excludes self-heating effects.
Note 8: Specified over the -40°C to +85°C temperature range.
Note 9: REFSEL[1:0] = 00 or when DACs are not powered up.
Note 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Note 11: The DAC buffers are guaranteed by design to be stable with a 1nF load.
Note 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Note 13: All DAC dynamic specifications are valid for a load of 100pF and 10k.
Note 14: Only one digital output (either DOUT,
EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Note 15: All digital inputs at either DVDD or DGND. DVDD should not exceed AVDD.
Note 16: See the
Reset Register section and Table 9 for details on programming the SLOW bit.
Note 17: Clock mode 11 only.
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