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參數(shù)資料
| 型號： | MAX1332ETE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, QCC16 |
| 封裝： | 3 X 3 MM, 0.8 MM HEIGHT, MO-220, TQFN-16 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 379K |
| 代理商： | MAX1332ETE |
enabled when using the buffered serial port to read the
data without μC intervention. Connect DV
DD
to the
TMS320C54_ supply voltage.
The MAX1332/MAX1333 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the transmit clock (CLKX) generated
internally to drive SCLK. A pullup resistor is required on
the CNVST signal to keep it high when DX goes high
impedance and write (0001)h to the data transmit regis-
ter (DXR) continuously for continuous conversions. The
power-down modes can be entered by writing (00FF)h
to the DXR (see Figures 17 and 18).
DSP Interface to the ADSP21_ _ _
The MAX1332/MAX1333 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices.
Figure 19 shows the direct connection of the
MAX1332/MAX1333 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to inter-
face with the MAX1332/MAX1333. For continuous con-
versions, idle CNVST low and pulse it high for one
clock cycle during the LSB of the previous transmitted
word. Configure the ADSP21_ _ _ STCTL and SRCTL
registers for early framing (LAFR = 0) and for an active-
high frame (LTFS = 0, LRFS = 0) signal. In this mode,
the data-independent frame-sync bit (DITFS = 1) can
be selected to eliminate the need for writing to the
transmit data register more than once. For single con-
versions, idle CNVST high and pulse it low for the entire
conversion. Configure the ADSP21_ _ _ STCTL and
SRCTL registers for late framing (LAFR = 1) and for an
active-low frame (LTFS = 1, LRFS = 1) signal. This is
also the best way to enter the power-down modes by
setting the word length to 8 bits (SLEN = 0111).
Connect the DV
DD
pin to the ADSP21_ _ _ supply volt-
age (see Figures 17 and 18).
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap
boards must not be used. Board layout must ensure
that digital and analog signal lines are separated from
each other. Do not run analog and digital (especially
clock) lines parallel to one another, or digital lines
underneath the ADC package.
Figure 20 shows the recommended system ground
connections. Establish an analog ground point at
AGND and a digital ground point at DGND. Connect all
other analog grounds to the analog ground point.
M
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
______________________________________________________________________________________
21
0
0
0
0
D11
D0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DOUT
SCLK
CNVST
0
0
D0
1
16
1
8
Figure 17. DSP Interface—Continuous Conversion
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DOUT
SCLK
CNVST
0
0
0
D0
1
1
Figure 18. DSP Interface—Single Conversion—Continuous/Burst Clock
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