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參數(shù)資料
| 型號(hào)： | MAX1332ETE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, QCC16 |
| 封裝： | 3 X 3 MM, 0.8 MM HEIGHT, MO-220, TQFN-16 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 379K |
| 代理商： | MAX1332ETE |
M
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
12
______________________________________________________________________________________
Pin Description
PIN
1
2
3
4
NAME
AIN0P
AIN0N
AIN1P
AIN1N
FUNCTION
Positive Analog-Input Channel 0
Negative Analog-Input Channel 0
Positive Analog-Input Channel 1
Negative Analog-Input Channel 1
5
REF
External Reference Voltage Input. V
REF
= 1V to (AV
DD
+ 50mV). Bypass REF to AGND with a 0.1μF
and a 1μF.
6
SHDN
Shutdown Input. Pull
SHDN
low to enter full power-down mode. Drive
SHDN
high to resume normal
operation regardless of previous software entered into power-down mode.
7
BIP/
UNI
Analog-Input-Mode Select. Drive BIP/
UNI
high to select bipolar-input mode. Pull BIP/
UNI
low to select
unipolar-input mode.
8
9
AGND
CHSEL
Analog Ground. Connect all AGNDs and EP to the same potential.
Channel-Select Input. Drive CHSEL high to select channel 1. Pull CHSEL low to select channel 0.
10
CNVST
Conversion-Start Input. The first rising edge of CNVST powers up the MAX1332/MAX1333 and begins
acquiring the analog input. A falling edge samples the analog input and starts a conversion. CNVST
also controls the power-down mode of the device (see the
Partial Power-Down (PPD) and Full Power-
Down (FPD) Mode
section).
11
SCLK
Serial-Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
12
DOUT
Serial-Data Output. Data is clocked out on the rising edge of SCLK
(see the
Starting a Conversion
section).
13
DV
DD
Positive-Digital-Supply Input. DV
DD
is the positive supply input for the digital section of the
MAX1332/MAX1333. Connect DV
DD
to a 2.7V to 3.6V power supply. Bypass DV
DD
to DGND with a
0.1μF capacitor in parallel with a 1μF capacitor. Place the bypass capacitors as close to the device
as possible.
14
DGND
Digital Ground. Ensure that the potential difference between AGND and DGND is less than ±0.3V.
15
AV
DD
Positive-Analog-Supply Input. AV
DD
is the positive supply input for the analog section of the
MAX1332/MAX1333. Connect AV
DD
to a 4.75V to 5.25V power supply for the MAX1332. Connect
AV
DD
to a 2.7V to 3.6V power supply for the MAX1333. Bypass AV
DD
to AGND with a 0.1μF capacitor
in parallel with a 1μF capacitor. Place the bypass capacitors as close to the device as possible.
16
—
AGND
EP
Analog Ground. Connect all AGNDs and EP to the same potential.
E xp osed P ad d e. Inter nal y connected to AGN D C onnect the exp osed p ad d e to the anal og g ound p ane.
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