參數(shù)資料
型號(hào): MAX1332
廠商: Maxim Integrated Products, Inc.
英文描述: 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs
中文描述: 3Msps/2Msps,5V/3V,雙通道,真差分12位ADC
文件頁(yè)數(shù): 4/25頁(yè)
文件大?。?/td> 379K
代理商: MAX1332
M
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (MAX1332) (continued)
(AV
DD
= +4.75V to +5.25V, DV
DD
= +2.7V to +3.6V, f
SCLK
= 48MHz, V
REF
= 4.096V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Average current (f
SAMPLE
= 3MHz, f
SCLK
=
48MHz, zero-scale input)
4.5
7
mA
Power-down (f
SCLK
= 48MHz), CNVST =
DV
DD
15
30
Digital Supply Current
I
DVDD
Static; all digital inputs are connected to
DV
DD
or DGND
AV
DD
= 4.75V to 5.25V, full-scale input
0.2
2
μA
Power-Supply Rejection
PSR
±2
mV
TIMING CHARACTERISTICS (MAX1332) (Figure 4)
(AV
DD
= +4.75V to +5.25V, DV
DD
= +2.7V to +3.6V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
t
CP
t
SPW
t
CRDD
t
CFDE
t
CHCF
t
BUCF
t
CFCH
t
CFBU
t
DHOLD
t
DOT
t
SETUP
t
HOLD
t
CSW
CONDITIONS
MIN
20.8
6
15
15
40
40
0
0
1
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Clock Period
SCLK Pulse Width
CNVST Rise to DOUT Disable
CNVST Fall to DOUT Enable
CHSEL to CNVST Fall Setup
BIP/
UNI
to CNVST Fall Setup
CNVST Fall to CHSEL Hold
SCLK Fall to BIP/
UNI
Hold
DOUT Remains Valid After SCLK
SCLK Rise to DOUT Transition
CNVST to SCLK Rise
SCLK Rise to CNVST
CNVST Pulse Width
C
LOAD
= 0pF (Note 2)
C
LOAD
= 30pF
2
6
6
0
6
Minimum Recovery Time (Full
Power-Down)
t
FPD
From CNVST fall or
SHDN
rise
4
μs
Minimum Recovery Time (Partial
Power-Down)
t
PPD
From CNVST fall
500
ns
Note 1:
Tested with AV
DD
= 4.75V and DV
DD
= +2.7V.
Note 2:
Guaranteed by design, not production tested.
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